335 lines
12 KiB
VHDL
335 lines
12 KiB
VHDL
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.92
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-- \ \ Application : MIG
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-- / / Filename : memc3_infrastructure.vhd
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-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
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-- \ \ / \ Date Created : Jul 03 2009
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-- \___\/\___\
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--
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--Device : Spartan-6
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--Design Name : DDR/DDR2/DDR3/LPDDR
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--Purpose : Clock generation/distribution and reset synchronization
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--Reference :
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--Revision History :
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library unisim;
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use unisim.vcomponents.all;
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entity memc3_infrastructure is
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generic
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(
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C_INCLK_PERIOD : integer := 2500;
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C_RST_ACT_LOW : integer := 1;
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C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
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C_CLKOUT0_DIVIDE : integer := 1;
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C_CLKOUT1_DIVIDE : integer := 1;
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C_CLKOUT2_DIVIDE : integer := 16;
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C_CLKOUT3_DIVIDE : integer := 8;
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C_CLKFBOUT_MULT : integer := 2;
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C_DIVCLK_DIVIDE : integer := 1
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);
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port
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(
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sys_clk_p : in std_logic;
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sys_clk_n : in std_logic;
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sys_clk : in std_logic;
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sys_rst_i : in std_logic;
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clk0 : out std_logic;
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rst0 : out std_logic;
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async_rst : out std_logic;
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sysclk_2x : out std_logic;
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sysclk_2x_180 : out std_logic;
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mcb_drp_clk : out std_logic;
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pll_ce_0 : out std_logic;
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pll_ce_90 : out std_logic;
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pll_lock : out std_logic
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);
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end entity;
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architecture syn of memc3_infrastructure is
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-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
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-- high number not so much for metastability protection, but to give time
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-- for reset (i.e. stable clock cycles) to propagate through all state
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-- machines and to all control signals (i.e. not all control signals have
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-- resets, instead they rely on base state logic being reset, and the effect
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-- of that reset propagating through the logic). Need this because we may not
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-- be getting stable clock cycles while reset asserted (i.e. since reset
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-- depends on PLL/DCM lock status)
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constant RST_SYNC_NUM : integer := 25;
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constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
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constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
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signal clk_2x_0 : std_logic;
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signal clk_2x_180 : std_logic;
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signal clk0_bufg : std_logic;
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signal clk0_bufg_in : std_logic;
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signal mcb_drp_clk_bufg_in : std_logic;
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signal clkfbout_clkfbin : std_logic;
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signal rst_tmp : std_logic;
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signal sys_clk_ibufg : std_logic;
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signal sys_rst : std_logic;
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signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
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signal powerup_pll_locked : std_logic;
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signal syn_clk0_powerup_pll_locked : std_logic;
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signal locked : std_logic;
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signal bufpll_mcb_locked : std_logic;
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signal mcb_drp_clk_sig : std_logic;
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attribute max_fanout : string;
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attribute syn_maxfan : integer;
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attribute KEEP : string;
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attribute max_fanout of rst0_sync_r : signal is "10";
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attribute syn_maxfan of rst0_sync_r : signal is 10;
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attribute KEEP of sys_clk_ibufg : signal is "TRUE";
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begin
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sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
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clk0 <= clk0_bufg;
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pll_lock <= bufpll_mcb_locked;
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mcb_drp_clk <= mcb_drp_clk_sig;
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diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
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--***********************************************************************
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-- Differential input clock input buffers
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--***********************************************************************
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u_ibufg_sys_clk : IBUFGDS
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generic map (
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DIFF_TERM => TRUE
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)
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port map (
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I => sys_clk_p,
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IB => sys_clk_n,
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O => sys_clk_ibufg
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);
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end generate;
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se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
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--***********************************************************************
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-- SINGLE_ENDED input clock input buffers
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--***********************************************************************
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u_ibufg_sys_clk : IBUFG
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port map (
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I => sys_clk,
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O => sys_clk_ibufg
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);
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end generate;
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--***************************************************************************
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-- Global clock generation and distribution
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--***************************************************************************
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u_pll_adv : PLL_ADV
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generic map
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(
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BANDWIDTH => "OPTIMIZED",
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CLKIN1_PERIOD => CLK_PERIOD_NS,
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CLKIN2_PERIOD => CLK_PERIOD_NS,
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CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
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CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
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CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
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CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
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CLKOUT4_DIVIDE => 1,
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CLKOUT5_DIVIDE => 1,
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CLKOUT0_PHASE => 0.000,
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CLKOUT1_PHASE => 180.000,
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CLKOUT2_PHASE => 0.000,
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CLKOUT3_PHASE => 0.000,
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CLKOUT4_PHASE => 0.000,
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CLKOUT5_PHASE => 0.000,
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CLKOUT0_DUTY_CYCLE => 0.500,
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CLKOUT1_DUTY_CYCLE => 0.500,
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CLKOUT2_DUTY_CYCLE => 0.500,
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CLKOUT3_DUTY_CYCLE => 0.500,
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CLKOUT4_DUTY_CYCLE => 0.500,
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CLKOUT5_DUTY_CYCLE => 0.500,
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SIM_DEVICE => "SPARTAN6",
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COMPENSATION => "INTERNAL",
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DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
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CLKFBOUT_MULT => C_CLKFBOUT_MULT,
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CLKFBOUT_PHASE => 0.0,
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REF_JITTER => 0.005000
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)
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port map
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(
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CLKFBIN => clkfbout_clkfbin,
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CLKINSEL => '1',
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CLKIN1 => sys_clk_ibufg,
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CLKIN2 => '0',
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DADDR => (others => '0'),
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DCLK => '0',
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DEN => '0',
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DI => (others => '0'),
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DWE => '0',
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REL => '0',
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RST => sys_rst,
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CLKFBDCM => open,
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CLKFBOUT => clkfbout_clkfbin,
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CLKOUTDCM0 => open,
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CLKOUTDCM1 => open,
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CLKOUTDCM2 => open,
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CLKOUTDCM3 => open,
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CLKOUTDCM4 => open,
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CLKOUTDCM5 => open,
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CLKOUT0 => clk_2x_0,
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CLKOUT1 => clk_2x_180,
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CLKOUT2 => clk0_bufg_in,
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CLKOUT3 => mcb_drp_clk_bufg_in,
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CLKOUT4 => open,
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CLKOUT5 => open,
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DO => open,
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DRDY => open,
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LOCKED => locked
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);
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U_BUFG_CLK0 : BUFG
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port map
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(
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O => clk0_bufg,
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I => clk0_bufg_in
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);
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--U_BUFG_CLK1 : BUFG
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-- port map (
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-- O => mcb_drp_clk_sig,
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-- I => mcb_drp_clk_bufg_in
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-- );
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U_BUFG_CLK1 : BUFGCE
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port map (
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O => mcb_drp_clk_sig,
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I => mcb_drp_clk_bufg_in,
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CE => locked
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);
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process (mcb_drp_clk_sig, sys_rst)
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begin
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if(sys_rst = '1') then
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powerup_pll_locked <= '0';
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elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
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if (bufpll_mcb_locked = '1') then
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powerup_pll_locked <= '1';
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end if;
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end if;
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end process;
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process (clk0_bufg, sys_rst)
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begin
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if(sys_rst = '1') then
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syn_clk0_powerup_pll_locked <= '0';
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elsif (clk0_bufg'event and clk0_bufg = '1') then
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if (bufpll_mcb_locked = '1') then
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syn_clk0_powerup_pll_locked <= '1';
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end if;
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end if;
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end process;
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--***************************************************************************
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-- Reset synchronization
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-- NOTES:
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-- 1. shut down the whole operation if the PLL hasn't yet locked (and
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-- by inference, this means that external sys_rst has been asserted -
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-- PLL deasserts LOCKED as soon as sys_rst asserted)
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-- 2. asynchronously assert reset. This was we can assert reset even if
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-- there is no clock (needed for things like 3-stating output buffers).
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-- reset deassertion is synchronous.
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-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
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-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
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-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
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-- enters suspend mode. We don't want reset to MCB get
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-- asserted in the application that needs suspend feature.
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--***************************************************************************
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async_rst <= sys_rst or not(powerup_pll_locked);
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-- async_rst <= rst_tmp;
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rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
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-- rst_tmp <= sys_rst or not(powerup_pll_locked);
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process (clk0_bufg, rst_tmp)
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begin
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if (rst_tmp = '1') then
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rst0_sync_r <= (others => '1');
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elsif (rising_edge(clk0_bufg)) then
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rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
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end if;
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end process;
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rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
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BUFPLL_MCB_INST : BUFPLL_MCB
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port map
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( IOCLK0 => sysclk_2x,
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IOCLK1 => sysclk_2x_180,
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LOCKED => locked,
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GCLK => mcb_drp_clk_sig,
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SERDESSTROBE0 => pll_ce_0,
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SERDESSTROBE1 => pll_ce_90,
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PLLIN0 => clk_2x_0,
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PLLIN1 => clk_2x_180,
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LOCK => bufpll_mcb_locked
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);
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end architecture syn;
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