1071 lines
45 KiB
VHDL
1071 lines
45 KiB
VHDL
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.92
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-- \ \ Application : MIG
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-- / / Filename : memc3_tb_top.vhd
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-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
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-- \ \ / \ Date Created : Jul 03 2009
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-- \___\/\___\
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--
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--Device : Spartan-6
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--Design Name : DDR/DDR2/DDR3/LPDDR
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--Purpose : This is top level module for test bench. which instantiates
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-- init_mem_pattern_ctr and mcb_traffic_gen modules for each user
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-- port.
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--Reference :
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--Revision History :
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity memc3_tb_top is
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generic
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(
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C_P0_MASK_SIZE : integer := 4;
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C_P0_DATA_PORT_SIZE : integer := 32;
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C_P1_MASK_SIZE : integer := 4;
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C_P1_DATA_PORT_SIZE : integer := 32;
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C_MEM_BURST_LEN : integer := 8;
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C_SIMULATION : string := "FALSE";
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C_MEM_NUM_COL_BITS : integer := 11;
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C_NUM_DQ_PINS : integer := 8;
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C_SMALL_DEVICE : string := "FALSE";
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C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
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C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
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C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
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C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
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C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100";
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C_p1_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000300";
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C_p1_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
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C_p1_END_ADDRESS : std_logic_vector(31 downto 0) := X"000004ff";
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C_p1_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
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C_p1_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000300";
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C_p2_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000500";
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C_p2_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
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C_p2_END_ADDRESS : std_logic_vector(31 downto 0) := X"000006ff";
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C_p2_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff800";
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C_p2_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000500";
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C_p3_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000700";
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C_p3_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
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C_p3_END_ADDRESS : std_logic_vector(31 downto 0) := X"000008ff";
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C_p3_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffff000";
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C_p3_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000700"
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);
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port
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(
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clk0 : in std_logic;
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rst0 : in std_logic;
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calib_done : in std_logic;
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p0_mcb_cmd_en_o : out std_logic;
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p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
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p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
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p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
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p0_mcb_cmd_full_i : in std_logic;
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p0_mcb_wr_en_o : out std_logic;
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p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
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p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
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p0_mcb_wr_full_i : in std_logic;
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p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
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p0_mcb_rd_en_o : out std_logic;
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p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
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p0_mcb_rd_empty_i : in std_logic;
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p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
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p1_mcb_cmd_en_o : out std_logic;
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p1_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
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p1_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
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p1_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
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p1_mcb_cmd_full_i : in std_logic;
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p1_mcb_wr_en_o : out std_logic;
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p1_mcb_wr_mask_o : out std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
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p1_mcb_wr_data_o : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
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p1_mcb_wr_full_i : in std_logic;
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p1_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
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p1_mcb_rd_en_o : out std_logic;
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p1_mcb_rd_data_i : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
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p1_mcb_rd_empty_i : in std_logic;
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p1_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
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p2_mcb_cmd_en_o : out std_logic;
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p2_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
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p2_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
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p2_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
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p2_mcb_cmd_full_i : in std_logic;
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p2_mcb_wr_en_o : out std_logic;
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p2_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
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p2_mcb_wr_data_o : out std_logic_vector(31 downto 0);
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p2_mcb_wr_full_i : in std_logic;
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p2_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
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p2_mcb_rd_en_o : out std_logic;
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p2_mcb_rd_data_i : in std_logic_vector(31 downto 0);
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p2_mcb_rd_empty_i : in std_logic;
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p2_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
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p3_mcb_cmd_en_o : out std_logic;
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p3_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
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p3_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
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p3_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
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p3_mcb_cmd_full_i : in std_logic;
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p3_mcb_wr_en_o : out std_logic;
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p3_mcb_wr_mask_o : out std_logic_vector(3 downto 0);
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p3_mcb_wr_data_o : out std_logic_vector(31 downto 0);
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p3_mcb_wr_full_i : in std_logic;
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p3_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
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p3_mcb_rd_en_o : out std_logic;
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p3_mcb_rd_data_i : in std_logic_vector(31 downto 0);
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p3_mcb_rd_empty_i : in std_logic;
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p3_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
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vio_modify_enable : in std_logic;
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vio_data_mode_value : in std_logic_vector(2 downto 0);
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vio_addr_mode_value : in std_logic_vector(2 downto 0);
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cmp_error : out std_logic;
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cmp_data : out std_logic_vector(31 downto 0);
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cmp_data_valid : out std_logic;
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error : out std_logic;
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error_status : out std_logic_vector(127 downto 0)
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);
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end memc3_tb_top;
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architecture arc of memc3_tb_top is
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function ERROR_DQWIDTH (val_i : integer) return integer is
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begin
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if (val_i = 4) then
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return 1;
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else
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return val_i/8;
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end if;
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end function ERROR_DQWIDTH;
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constant DQ_ERROR_WIDTH : integer := ERROR_DQWIDTH(C_NUM_DQ_PINS);
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component init_mem_pattern_ctr IS
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generic (
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FAMILY : string;
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BEGIN_ADDRESS : std_logic_vector(31 downto 0);
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END_ADDRESS : std_logic_vector(31 downto 0);
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DWIDTH : integer;
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CMD_SEED_VALUE : std_logic_vector(31 downto 0);
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DATA_SEED_VALUE : std_logic_vector(31 downto 0);
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DATA_MODE : std_logic_vector(3 downto 0);
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PORT_MODE : string
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);
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PORT (
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clk_i : in std_logic;
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rst_i : in std_logic;
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mcb_cmd_bl_i : in std_logic_vector(5 downto 0);
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mcb_cmd_en_i : in std_logic;
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mcb_cmd_instr_i : in std_logic_vector(2 downto 0);
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mcb_init_done_i : in std_logic;
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mcb_wr_en_i : in std_logic;
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vio_modify_enable : in std_logic;
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vio_data_mode_value : in std_logic_vector(2 downto 0);
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vio_addr_mode_value : in std_logic_vector(2 downto 0);
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vio_bl_mode_value : in STD_LOGIC_VECTOR(1 downto 0);
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vio_fixed_bl_value : in STD_LOGIC_VECTOR(5 downto 0);
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cmp_error : in std_logic;
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run_traffic_o : out std_logic;
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start_addr_o : out std_logic_vector(31 downto 0);
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end_addr_o : out std_logic_vector(31 downto 0);
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cmd_seed_o : out std_logic_vector(31 downto 0);
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data_seed_o : out std_logic_vector(31 downto 0);
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load_seed_o : out std_logic;
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addr_mode_o : out std_logic_vector(2 downto 0);
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instr_mode_o : out std_logic_vector(3 downto 0);
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bl_mode_o : out std_logic_vector(1 downto 0);
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data_mode_o : out std_logic_vector(3 downto 0);
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mode_load_o : out std_logic;
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fixed_bl_o : out std_logic_vector(5 downto 0);
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fixed_instr_o : out std_logic_vector(2 downto 0);
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fixed_addr_o : out std_logic_vector(31 downto 0)
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);
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end component;
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component mcb_traffic_gen is
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generic (
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FAMILY : string;
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SIMULATION : string;
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MEM_BURST_LEN : integer;
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PORT_MODE : string;
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DATA_PATTERN : string;
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CMD_PATTERN : string;
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ADDR_WIDTH : integer;
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CMP_DATA_PIPE_STAGES : integer;
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MEM_COL_WIDTH : integer;
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NUM_DQ_PINS : integer;
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DQ_ERROR_WIDTH : integer;
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DWIDTH : integer;
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PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
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PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0);
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PRBS_EADDR : std_logic_vector(31 downto 0);
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PRBS_SADDR : std_logic_vector(31 downto 0)
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic;
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run_traffic_i : in std_logic;
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manual_clear_error : in std_logic;
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-- *** runtime parameter ***
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start_addr_i : in std_logic_vector(31 downto 0);
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end_addr_i : in std_logic_vector(31 downto 0);
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cmd_seed_i : in std_logic_vector(31 downto 0);
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data_seed_i : in std_logic_vector(31 downto 0);
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load_seed_i : in std_logic;
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addr_mode_i : in std_logic_vector(2 downto 0);
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instr_mode_i : in std_logic_vector(3 downto 0);
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bl_mode_i : in std_logic_vector(1 downto 0);
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data_mode_i : in std_logic_vector(3 downto 0);
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mode_load_i : in std_logic;
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-- fixed pattern inputs interface
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fixed_bl_i : in std_logic_vector(5 downto 0);
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fixed_instr_i : in std_logic_vector(2 downto 0);
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fixed_addr_i : in std_logic_vector(31 downto 0);
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fixed_data_i : IN STD_LOGIC_VECTOR(DWIDTH-1 DOWNTO 0);
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bram_cmd_i : in std_logic_vector(38 downto 0);
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bram_valid_i : in std_logic;
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bram_rdy_o : out std_logic;
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--///////////////////////////////////////////////////////////////////////////
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-- MCB INTERFACE
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-- interface to mcb command port
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mcb_cmd_en_o : out std_logic;
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mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
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mcb_cmd_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
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mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
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mcb_cmd_full_i : in std_logic;
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-- interface to mcb wr data port
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mcb_wr_en_o : out std_logic;
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mcb_wr_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
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mcb_wr_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
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mcb_wr_data_end_o : OUT std_logic;
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mcb_wr_full_i : in std_logic;
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mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
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-- interface to mcb rd data port
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mcb_rd_en_o : out std_logic;
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mcb_rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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mcb_rd_empty_i : in std_logic;
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mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
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--///////////////////////////////////////////////////////////////////////////
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-- status feedback
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counts_rst : in std_logic;
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wr_data_counts : out std_logic_vector(47 downto 0);
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rd_data_counts : out std_logic_vector(47 downto 0);
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cmp_data : out std_logic_vector(DWIDTH - 1 downto 0);
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cmp_data_valid : out std_logic;
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cmp_error : out std_logic;
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error : out std_logic;
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error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
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mem_rd_data : out std_logic_vector(DWIDTH - 1 downto 0);
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dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
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cumlative_dq_lane_error : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
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);
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end component;
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-- Function to determine the number of data patterns to be generated
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function DATA_PATTERN_CALC return string is
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begin
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if (C_SMALL_DEVICE = "FALSE") then
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return "DGEN_ALL";
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else
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return "DGEN_ADDR";
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end if;
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end function;
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constant FAMILY : string := "SPARTAN6";
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constant DATA_PATTERN : string := DATA_PATTERN_CALC;
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constant CMD_PATTERN : string := "CGEN_ALL";
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constant ADDR_WIDTH : integer := 30;
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constant CMP_DATA_PIPE_STAGES : integer := 0;
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constant PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00007000";
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constant PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFF8000";
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constant PRBS_SADDR : std_logic_vector(31 downto 0) := X"00005000";
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constant PRBS_EADDR : std_logic_vector(31 downto 0) := X"00007fff";
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constant BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
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constant END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
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constant DATA_MODE : std_logic_vector(3 downto 0) := "0010";
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constant p0_DWIDTH : integer := 32;
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constant p1_DWIDTH : integer := 32;
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constant p2_DWIDTH : integer := 32;
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constant p3_DWIDTH : integer := 32;
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constant p0_PORT_MODE : string := "BI_MODE";
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constant p1_PORT_MODE : string := "BI_MODE";
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constant p2_PORT_MODE : string := "BI_MODE";
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constant p3_PORT_MODE : string := "BI_MODE";
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--p0 Signal declarations
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signal p0_tg_run_traffic : std_logic;
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signal p0_tg_start_addr : std_logic_vector(31 downto 0);
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signal p0_tg_end_addr : std_logic_vector(31 downto 0);
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signal p0_tg_cmd_seed : std_logic_vector(31 downto 0);
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signal p0_tg_data_seed : std_logic_vector(31 downto 0);
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signal p0_tg_load_seed : std_logic;
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signal p0_tg_addr_mode : std_logic_vector(2 downto 0);
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signal p0_tg_instr_mode : std_logic_vector(3 downto 0);
|
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signal p0_tg_bl_mode : std_logic_vector(1 downto 0);
|
|
signal p0_tg_data_mode : std_logic_vector(3 downto 0);
|
|
signal p0_tg_mode_load : std_logic;
|
|
signal p0_tg_fixed_bl : std_logic_vector(5 downto 0);
|
|
signal p0_tg_fixed_instr : std_logic_vector(2 downto 0);
|
|
signal p0_tg_fixed_addr : std_logic_vector(31 downto 0);
|
|
signal p0_error_status : std_logic_vector(64 + (2*p0_DWIDTH - 1) downto 0);
|
|
signal p0_error : std_logic;
|
|
signal p0_cmp_error : std_logic;
|
|
signal p0_cmp_data : std_logic_vector(p0_DWIDTH-1 downto 0);
|
|
signal p0_cmp_data_valid : std_logic;
|
|
|
|
signal p0_mcb_cmd_en_o_int : std_logic;
|
|
signal p0_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
|
|
signal p0_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
|
|
signal p0_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
|
|
signal p0_mcb_wr_en_o_int : std_logic;
|
|
|
|
|
|
--p1 Signal declarations
|
|
signal p1_tg_run_traffic : std_logic;
|
|
signal p1_tg_start_addr : std_logic_vector(31 downto 0);
|
|
signal p1_tg_end_addr : std_logic_vector(31 downto 0);
|
|
signal p1_tg_cmd_seed : std_logic_vector(31 downto 0);
|
|
signal p1_tg_data_seed : std_logic_vector(31 downto 0);
|
|
signal p1_tg_load_seed : std_logic;
|
|
signal p1_tg_addr_mode : std_logic_vector(2 downto 0);
|
|
signal p1_tg_instr_mode : std_logic_vector(3 downto 0);
|
|
signal p1_tg_bl_mode : std_logic_vector(1 downto 0);
|
|
signal p1_tg_data_mode : std_logic_vector(3 downto 0);
|
|
signal p1_tg_mode_load : std_logic;
|
|
signal p1_tg_fixed_bl : std_logic_vector(5 downto 0);
|
|
signal p1_tg_fixed_instr : std_logic_vector(2 downto 0);
|
|
signal p1_tg_fixed_addr : std_logic_vector(31 downto 0);
|
|
signal p1_error_status : std_logic_vector(64 + (2*p1_DWIDTH - 1) downto 0);
|
|
signal p1_error : std_logic;
|
|
signal p1_cmp_error : std_logic;
|
|
signal p1_cmp_data : std_logic_vector(p1_DWIDTH-1 downto 0);
|
|
signal p1_cmp_data_valid : std_logic;
|
|
|
|
signal p1_mcb_cmd_en_o_int : std_logic;
|
|
signal p1_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
|
|
signal p1_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
|
|
signal p1_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
|
|
signal p1_mcb_wr_en_o_int : std_logic;
|
|
|
|
|
|
--p2 Signal declarations
|
|
signal p2_tg_run_traffic : std_logic;
|
|
signal p2_tg_start_addr : std_logic_vector(31 downto 0);
|
|
signal p2_tg_end_addr : std_logic_vector(31 downto 0);
|
|
signal p2_tg_cmd_seed : std_logic_vector(31 downto 0);
|
|
signal p2_tg_data_seed : std_logic_vector(31 downto 0);
|
|
signal p2_tg_load_seed : std_logic;
|
|
signal p2_tg_addr_mode : std_logic_vector(2 downto 0);
|
|
signal p2_tg_instr_mode : std_logic_vector(3 downto 0);
|
|
signal p2_tg_bl_mode : std_logic_vector(1 downto 0);
|
|
signal p2_tg_data_mode : std_logic_vector(3 downto 0);
|
|
signal p2_tg_mode_load : std_logic;
|
|
signal p2_tg_fixed_bl : std_logic_vector(5 downto 0);
|
|
signal p2_tg_fixed_instr : std_logic_vector(2 downto 0);
|
|
signal p2_tg_fixed_addr : std_logic_vector(31 downto 0);
|
|
signal p2_error_status : std_logic_vector(64 + (2*p2_DWIDTH - 1) downto 0);
|
|
signal p2_error : std_logic;
|
|
signal p2_cmp_error : std_logic;
|
|
signal p2_cmp_data : std_logic_vector(p2_DWIDTH-1 downto 0);
|
|
signal p2_cmp_data_valid : std_logic;
|
|
|
|
signal p2_mcb_cmd_en_o_int : std_logic;
|
|
signal p2_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
|
|
signal p2_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
|
|
signal p2_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
|
|
signal p2_mcb_wr_en_o_int : std_logic;
|
|
|
|
|
|
--p3 Signal declarations
|
|
signal p3_tg_run_traffic : std_logic;
|
|
signal p3_tg_start_addr : std_logic_vector(31 downto 0);
|
|
signal p3_tg_end_addr : std_logic_vector(31 downto 0);
|
|
signal p3_tg_cmd_seed : std_logic_vector(31 downto 0);
|
|
signal p3_tg_data_seed : std_logic_vector(31 downto 0);
|
|
signal p3_tg_load_seed : std_logic;
|
|
signal p3_tg_addr_mode : std_logic_vector(2 downto 0);
|
|
signal p3_tg_instr_mode : std_logic_vector(3 downto 0);
|
|
signal p3_tg_bl_mode : std_logic_vector(1 downto 0);
|
|
signal p3_tg_data_mode : std_logic_vector(3 downto 0);
|
|
signal p3_tg_mode_load : std_logic;
|
|
signal p3_tg_fixed_bl : std_logic_vector(5 downto 0);
|
|
signal p3_tg_fixed_instr : std_logic_vector(2 downto 0);
|
|
signal p3_tg_fixed_addr : std_logic_vector(31 downto 0);
|
|
signal p3_error_status : std_logic_vector(64 + (2*p3_DWIDTH - 1) downto 0);
|
|
signal p3_error : std_logic;
|
|
signal p3_cmp_error : std_logic;
|
|
signal p3_cmp_data : std_logic_vector(p3_DWIDTH-1 downto 0);
|
|
signal p3_cmp_data_valid : std_logic;
|
|
|
|
signal p3_mcb_cmd_en_o_int : std_logic;
|
|
signal p3_mcb_cmd_instr_o_int : std_logic_vector(2 downto 0);
|
|
signal p3_mcb_cmd_bl_o_int : std_logic_vector(5 downto 0);
|
|
signal p3_mcb_cmd_addr_o_int : std_logic_vector(29 downto 0);
|
|
signal p3_mcb_wr_en_o_int : std_logic;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
--signal cmp_data : std_logic_vector(31 downto 0);
|
|
begin
|
|
|
|
cmp_error <= p0_cmp_error or p1_cmp_error or p2_cmp_error or p3_cmp_error;
|
|
error <= p0_error or p1_error or p2_error or p3_error;
|
|
error_status <= p0_error_status;
|
|
cmp_data <= p0_cmp_data(31 downto 0);
|
|
cmp_data_valid <= p0_cmp_data_valid;
|
|
|
|
|
|
p0_mcb_cmd_en_o <= p0_mcb_cmd_en_o_int;
|
|
p0_mcb_cmd_instr_o <= p0_mcb_cmd_instr_o_int;
|
|
p0_mcb_cmd_bl_o <= p0_mcb_cmd_bl_o_int;
|
|
p0_mcb_cmd_addr_o <= p0_mcb_cmd_addr_o_int;
|
|
p0_mcb_wr_en_o <= p0_mcb_wr_en_o_int;
|
|
|
|
init_mem_pattern_ctr_p0 :init_mem_pattern_ctr
|
|
generic map
|
|
(
|
|
DWIDTH => p0_DWIDTH,
|
|
FAMILY => FAMILY,
|
|
BEGIN_ADDRESS => C_p0_BEGIN_ADDRESS,
|
|
END_ADDRESS => C_p0_END_ADDRESS,
|
|
CMD_SEED_VALUE => X"56456783",
|
|
DATA_SEED_VALUE => X"12345678",
|
|
DATA_MODE => C_p0_DATA_MODE,
|
|
PORT_MODE => p0_PORT_MODE
|
|
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
|
|
mcb_cmd_en_i => p0_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_i => p0_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_i => p0_mcb_cmd_bl_o_int,
|
|
mcb_wr_en_i => p0_mcb_wr_en_o_int,
|
|
|
|
vio_modify_enable => vio_modify_enable,
|
|
vio_data_mode_value => vio_data_mode_value,
|
|
vio_addr_mode_value => vio_addr_mode_value,
|
|
vio_bl_mode_value => "10",--vio_bl_mode_value,
|
|
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
|
|
|
|
mcb_init_done_i => calib_done,
|
|
cmp_error => p0_error,
|
|
run_traffic_o => p0_tg_run_traffic,
|
|
start_addr_o => p0_tg_start_addr,
|
|
end_addr_o => p0_tg_end_addr ,
|
|
cmd_seed_o => p0_tg_cmd_seed ,
|
|
data_seed_o => p0_tg_data_seed ,
|
|
load_seed_o => p0_tg_load_seed ,
|
|
addr_mode_o => p0_tg_addr_mode ,
|
|
instr_mode_o => p0_tg_instr_mode ,
|
|
bl_mode_o => p0_tg_bl_mode ,
|
|
data_mode_o => p0_tg_data_mode ,
|
|
mode_load_o => p0_tg_mode_load ,
|
|
fixed_bl_o => p0_tg_fixed_bl ,
|
|
fixed_instr_o => p0_tg_fixed_instr,
|
|
fixed_addr_o => p0_tg_fixed_addr
|
|
);
|
|
|
|
m_traffic_gen_p0 : mcb_traffic_gen
|
|
generic map(
|
|
MEM_BURST_LEN => C_MEM_BURST_LEN,
|
|
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
|
|
NUM_DQ_PINS => C_NUM_DQ_PINS,
|
|
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
|
|
|
|
PORT_MODE => p0_PORT_MODE,
|
|
DWIDTH => p0_DWIDTH,
|
|
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
|
|
FAMILY => FAMILY,
|
|
SIMULATION => "FALSE",
|
|
DATA_PATTERN => DATA_PATTERN,
|
|
CMD_PATTERN => "CGEN_ALL",
|
|
ADDR_WIDTH => 30,
|
|
PRBS_SADDR_MASK_POS => C_p0_PRBS_SADDR_MASK_POS,
|
|
PRBS_EADDR_MASK_POS => C_p0_PRBS_EADDR_MASK_POS,
|
|
PRBS_SADDR => C_p0_BEGIN_ADDRESS,
|
|
PRBS_EADDR => C_p0_END_ADDRESS
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
run_traffic_i => p0_tg_run_traffic,
|
|
manual_clear_error => rst0,
|
|
-- runtime parameter
|
|
start_addr_i => p0_tg_start_addr ,
|
|
end_addr_i => p0_tg_end_addr ,
|
|
cmd_seed_i => p0_tg_cmd_seed ,
|
|
data_seed_i => p0_tg_data_seed ,
|
|
load_seed_i => p0_tg_load_seed,
|
|
addr_mode_i => p0_tg_addr_mode,
|
|
|
|
instr_mode_i => p0_tg_instr_mode ,
|
|
bl_mode_i => p0_tg_bl_mode ,
|
|
data_mode_i => p0_tg_data_mode ,
|
|
mode_load_i => p0_tg_mode_load ,
|
|
|
|
-- fixed pattern inputs interface
|
|
fixed_bl_i => p0_tg_fixed_bl,
|
|
fixed_instr_i => p0_tg_fixed_instr,
|
|
fixed_addr_i => p0_tg_fixed_addr,
|
|
fixed_data_i => (others => '0'),
|
|
-- BRAM interface.
|
|
bram_cmd_i => (others => '0'),
|
|
bram_valid_i => '0',
|
|
bram_rdy_o => open,
|
|
|
|
-- MCB INTERFACE
|
|
mcb_cmd_en_o => p0_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_o => p0_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_o => p0_mcb_cmd_bl_o_int,
|
|
mcb_cmd_addr_o => p0_mcb_cmd_addr_o_int,
|
|
mcb_cmd_full_i => p0_mcb_cmd_full_i,
|
|
|
|
mcb_wr_en_o => p0_mcb_wr_en_o_int,
|
|
mcb_wr_mask_o => p0_mcb_wr_mask_o,
|
|
mcb_wr_data_o => p0_mcb_wr_data_o,
|
|
mcb_wr_data_end_o => open,
|
|
mcb_wr_full_i => p0_mcb_wr_full_i,
|
|
mcb_wr_fifo_counts => p0_mcb_wr_fifo_counts,
|
|
|
|
mcb_rd_en_o => p0_mcb_rd_en_o,
|
|
mcb_rd_data_i => p0_mcb_rd_data_i,
|
|
mcb_rd_empty_i => p0_mcb_rd_empty_i,
|
|
mcb_rd_fifo_counts => p0_mcb_rd_fifo_counts,
|
|
|
|
-- status feedback
|
|
counts_rst => rst0,
|
|
wr_data_counts => open,
|
|
rd_data_counts => open,
|
|
cmp_data => p0_cmp_data,
|
|
cmp_data_valid => p0_cmp_data_valid,
|
|
cmp_error => p0_cmp_error,
|
|
error => p0_error,
|
|
error_status => p0_error_status,
|
|
mem_rd_data => open,
|
|
dq_error_bytelane_cmp => open,
|
|
cumlative_dq_lane_error => open
|
|
);
|
|
|
|
|
|
|
|
p1_mcb_cmd_en_o <= p1_mcb_cmd_en_o_int;
|
|
p1_mcb_cmd_instr_o <= p1_mcb_cmd_instr_o_int;
|
|
p1_mcb_cmd_bl_o <= p1_mcb_cmd_bl_o_int;
|
|
p1_mcb_cmd_addr_o <= p1_mcb_cmd_addr_o_int;
|
|
p1_mcb_wr_en_o <= p1_mcb_wr_en_o_int;
|
|
|
|
init_mem_pattern_ctr_p1 :init_mem_pattern_ctr
|
|
generic map
|
|
(
|
|
DWIDTH => p1_DWIDTH,
|
|
FAMILY => FAMILY,
|
|
BEGIN_ADDRESS => C_p1_BEGIN_ADDRESS,
|
|
END_ADDRESS => C_p1_END_ADDRESS,
|
|
CMD_SEED_VALUE => X"56456783",
|
|
DATA_SEED_VALUE => X"12345678",
|
|
DATA_MODE => C_p1_DATA_MODE,
|
|
PORT_MODE => p1_PORT_MODE
|
|
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
|
|
mcb_cmd_en_i => p1_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_i => p1_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_i => p1_mcb_cmd_bl_o_int,
|
|
mcb_wr_en_i => p1_mcb_wr_en_o_int,
|
|
|
|
vio_modify_enable => vio_modify_enable,
|
|
vio_data_mode_value => vio_data_mode_value,
|
|
vio_addr_mode_value => vio_addr_mode_value,
|
|
vio_bl_mode_value => "10",--vio_bl_mode_value,
|
|
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
|
|
|
|
mcb_init_done_i => calib_done,
|
|
cmp_error => p1_error,
|
|
run_traffic_o => p1_tg_run_traffic,
|
|
start_addr_o => p1_tg_start_addr,
|
|
end_addr_o => p1_tg_end_addr ,
|
|
cmd_seed_o => p1_tg_cmd_seed ,
|
|
data_seed_o => p1_tg_data_seed ,
|
|
load_seed_o => p1_tg_load_seed ,
|
|
addr_mode_o => p1_tg_addr_mode ,
|
|
instr_mode_o => p1_tg_instr_mode ,
|
|
bl_mode_o => p1_tg_bl_mode ,
|
|
data_mode_o => p1_tg_data_mode ,
|
|
mode_load_o => p1_tg_mode_load ,
|
|
fixed_bl_o => p1_tg_fixed_bl ,
|
|
fixed_instr_o => p1_tg_fixed_instr,
|
|
fixed_addr_o => p1_tg_fixed_addr
|
|
);
|
|
|
|
m_traffic_gen_p1 : mcb_traffic_gen
|
|
generic map(
|
|
MEM_BURST_LEN => C_MEM_BURST_LEN,
|
|
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
|
|
NUM_DQ_PINS => C_NUM_DQ_PINS,
|
|
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
|
|
|
|
PORT_MODE => p1_PORT_MODE,
|
|
DWIDTH => p1_DWIDTH,
|
|
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
|
|
FAMILY => FAMILY,
|
|
SIMULATION => "FALSE",
|
|
DATA_PATTERN => DATA_PATTERN,
|
|
CMD_PATTERN => "CGEN_ALL",
|
|
ADDR_WIDTH => 30,
|
|
PRBS_SADDR_MASK_POS => C_p1_PRBS_SADDR_MASK_POS,
|
|
PRBS_EADDR_MASK_POS => C_p1_PRBS_EADDR_MASK_POS,
|
|
PRBS_SADDR => C_p1_BEGIN_ADDRESS,
|
|
PRBS_EADDR => C_p1_END_ADDRESS
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
run_traffic_i => p1_tg_run_traffic,
|
|
manual_clear_error => rst0,
|
|
-- runtime parameter
|
|
start_addr_i => p1_tg_start_addr ,
|
|
end_addr_i => p1_tg_end_addr ,
|
|
cmd_seed_i => p1_tg_cmd_seed ,
|
|
data_seed_i => p1_tg_data_seed ,
|
|
load_seed_i => p1_tg_load_seed,
|
|
addr_mode_i => p1_tg_addr_mode,
|
|
|
|
instr_mode_i => p1_tg_instr_mode ,
|
|
bl_mode_i => p1_tg_bl_mode ,
|
|
data_mode_i => p1_tg_data_mode ,
|
|
mode_load_i => p1_tg_mode_load ,
|
|
|
|
-- fixed pattern inputs interface
|
|
fixed_bl_i => p1_tg_fixed_bl,
|
|
fixed_instr_i => p1_tg_fixed_instr,
|
|
fixed_addr_i => p1_tg_fixed_addr,
|
|
fixed_data_i => (others => '0'),
|
|
-- BRAM interface.
|
|
bram_cmd_i => (others => '0'),
|
|
bram_valid_i => '0',
|
|
bram_rdy_o => open,
|
|
|
|
-- MCB INTERFACE
|
|
mcb_cmd_en_o => p1_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_o => p1_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_o => p1_mcb_cmd_bl_o_int,
|
|
mcb_cmd_addr_o => p1_mcb_cmd_addr_o_int,
|
|
mcb_cmd_full_i => p1_mcb_cmd_full_i,
|
|
|
|
mcb_wr_en_o => p1_mcb_wr_en_o_int,
|
|
mcb_wr_mask_o => p1_mcb_wr_mask_o,
|
|
mcb_wr_data_o => p1_mcb_wr_data_o,
|
|
mcb_wr_data_end_o => open,
|
|
mcb_wr_full_i => p1_mcb_wr_full_i,
|
|
mcb_wr_fifo_counts => p1_mcb_wr_fifo_counts,
|
|
|
|
mcb_rd_en_o => p1_mcb_rd_en_o,
|
|
mcb_rd_data_i => p1_mcb_rd_data_i,
|
|
mcb_rd_empty_i => p1_mcb_rd_empty_i,
|
|
mcb_rd_fifo_counts => p1_mcb_rd_fifo_counts,
|
|
|
|
-- status feedback
|
|
counts_rst => rst0,
|
|
wr_data_counts => open,
|
|
rd_data_counts => open,
|
|
cmp_data => p1_cmp_data,
|
|
cmp_data_valid => p1_cmp_data_valid,
|
|
cmp_error => p1_cmp_error,
|
|
error => p1_error,
|
|
error_status => p1_error_status,
|
|
mem_rd_data => open,
|
|
dq_error_bytelane_cmp => open,
|
|
cumlative_dq_lane_error => open
|
|
);
|
|
|
|
|
|
|
|
p2_mcb_cmd_en_o <= p2_mcb_cmd_en_o_int;
|
|
p2_mcb_cmd_instr_o <= p2_mcb_cmd_instr_o_int;
|
|
p2_mcb_cmd_bl_o <= p2_mcb_cmd_bl_o_int;
|
|
p2_mcb_cmd_addr_o <= p2_mcb_cmd_addr_o_int;
|
|
p2_mcb_wr_en_o <= p2_mcb_wr_en_o_int;
|
|
|
|
init_mem_pattern_ctr_p2 :init_mem_pattern_ctr
|
|
generic map
|
|
(
|
|
DWIDTH => p2_DWIDTH,
|
|
FAMILY => FAMILY,
|
|
BEGIN_ADDRESS => C_p2_BEGIN_ADDRESS,
|
|
END_ADDRESS => C_p2_END_ADDRESS,
|
|
CMD_SEED_VALUE => X"56456783",
|
|
DATA_SEED_VALUE => X"12345678",
|
|
DATA_MODE => C_p2_DATA_MODE,
|
|
PORT_MODE => p2_PORT_MODE
|
|
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
|
|
mcb_cmd_en_i => p2_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_i => p2_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_i => p2_mcb_cmd_bl_o_int,
|
|
mcb_wr_en_i => p2_mcb_wr_en_o_int,
|
|
|
|
vio_modify_enable => vio_modify_enable,
|
|
vio_data_mode_value => vio_data_mode_value,
|
|
vio_addr_mode_value => vio_addr_mode_value,
|
|
vio_bl_mode_value => "10",--vio_bl_mode_value,
|
|
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
|
|
|
|
mcb_init_done_i => calib_done,
|
|
cmp_error => p2_error,
|
|
run_traffic_o => p2_tg_run_traffic,
|
|
start_addr_o => p2_tg_start_addr,
|
|
end_addr_o => p2_tg_end_addr ,
|
|
cmd_seed_o => p2_tg_cmd_seed ,
|
|
data_seed_o => p2_tg_data_seed ,
|
|
load_seed_o => p2_tg_load_seed ,
|
|
addr_mode_o => p2_tg_addr_mode ,
|
|
instr_mode_o => p2_tg_instr_mode ,
|
|
bl_mode_o => p2_tg_bl_mode ,
|
|
data_mode_o => p2_tg_data_mode ,
|
|
mode_load_o => p2_tg_mode_load ,
|
|
fixed_bl_o => p2_tg_fixed_bl ,
|
|
fixed_instr_o => p2_tg_fixed_instr,
|
|
fixed_addr_o => p2_tg_fixed_addr
|
|
);
|
|
|
|
m_traffic_gen_p2 : mcb_traffic_gen
|
|
generic map(
|
|
MEM_BURST_LEN => C_MEM_BURST_LEN,
|
|
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
|
|
NUM_DQ_PINS => C_NUM_DQ_PINS,
|
|
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
|
|
|
|
PORT_MODE => p2_PORT_MODE,
|
|
DWIDTH => p2_DWIDTH,
|
|
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
|
|
FAMILY => FAMILY,
|
|
SIMULATION => "FALSE",
|
|
DATA_PATTERN => DATA_PATTERN,
|
|
CMD_PATTERN => "CGEN_ALL",
|
|
ADDR_WIDTH => 30,
|
|
PRBS_SADDR_MASK_POS => C_p2_PRBS_SADDR_MASK_POS,
|
|
PRBS_EADDR_MASK_POS => C_p2_PRBS_EADDR_MASK_POS,
|
|
PRBS_SADDR => C_p2_BEGIN_ADDRESS,
|
|
PRBS_EADDR => C_p2_END_ADDRESS
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
run_traffic_i => p2_tg_run_traffic,
|
|
manual_clear_error => rst0,
|
|
-- runtime parameter
|
|
start_addr_i => p2_tg_start_addr ,
|
|
end_addr_i => p2_tg_end_addr ,
|
|
cmd_seed_i => p2_tg_cmd_seed ,
|
|
data_seed_i => p2_tg_data_seed ,
|
|
load_seed_i => p2_tg_load_seed,
|
|
addr_mode_i => p2_tg_addr_mode,
|
|
|
|
instr_mode_i => p2_tg_instr_mode ,
|
|
bl_mode_i => p2_tg_bl_mode ,
|
|
data_mode_i => p2_tg_data_mode ,
|
|
mode_load_i => p2_tg_mode_load ,
|
|
|
|
-- fixed pattern inputs interface
|
|
fixed_bl_i => p2_tg_fixed_bl,
|
|
fixed_instr_i => p2_tg_fixed_instr,
|
|
fixed_addr_i => p2_tg_fixed_addr,
|
|
fixed_data_i => (others => '0'),
|
|
-- BRAM interface.
|
|
bram_cmd_i => (others => '0'),
|
|
bram_valid_i => '0',
|
|
bram_rdy_o => open,
|
|
|
|
-- MCB INTERFACE
|
|
mcb_cmd_en_o => p2_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_o => p2_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_o => p2_mcb_cmd_bl_o_int,
|
|
mcb_cmd_addr_o => p2_mcb_cmd_addr_o_int,
|
|
mcb_cmd_full_i => p2_mcb_cmd_full_i,
|
|
|
|
mcb_wr_en_o => p2_mcb_wr_en_o_int,
|
|
mcb_wr_mask_o => p2_mcb_wr_mask_o,
|
|
mcb_wr_data_o => p2_mcb_wr_data_o,
|
|
mcb_wr_data_end_o => open,
|
|
mcb_wr_full_i => p2_mcb_wr_full_i,
|
|
mcb_wr_fifo_counts => p2_mcb_wr_fifo_counts,
|
|
|
|
mcb_rd_en_o => p2_mcb_rd_en_o,
|
|
mcb_rd_data_i => p2_mcb_rd_data_i,
|
|
mcb_rd_empty_i => p2_mcb_rd_empty_i,
|
|
mcb_rd_fifo_counts => p2_mcb_rd_fifo_counts,
|
|
|
|
-- status feedback
|
|
counts_rst => rst0,
|
|
wr_data_counts => open,
|
|
rd_data_counts => open,
|
|
cmp_data => p2_cmp_data,
|
|
cmp_data_valid => p2_cmp_data_valid,
|
|
cmp_error => p2_cmp_error,
|
|
error => p2_error,
|
|
error_status => p2_error_status,
|
|
mem_rd_data => open,
|
|
dq_error_bytelane_cmp => open,
|
|
cumlative_dq_lane_error => open
|
|
);
|
|
|
|
|
|
|
|
p3_mcb_cmd_en_o <= p3_mcb_cmd_en_o_int;
|
|
p3_mcb_cmd_instr_o <= p3_mcb_cmd_instr_o_int;
|
|
p3_mcb_cmd_bl_o <= p3_mcb_cmd_bl_o_int;
|
|
p3_mcb_cmd_addr_o <= p3_mcb_cmd_addr_o_int;
|
|
p3_mcb_wr_en_o <= p3_mcb_wr_en_o_int;
|
|
|
|
init_mem_pattern_ctr_p3 :init_mem_pattern_ctr
|
|
generic map
|
|
(
|
|
DWIDTH => p3_DWIDTH,
|
|
FAMILY => FAMILY,
|
|
BEGIN_ADDRESS => C_p3_BEGIN_ADDRESS,
|
|
END_ADDRESS => C_p3_END_ADDRESS,
|
|
CMD_SEED_VALUE => X"56456783",
|
|
DATA_SEED_VALUE => X"12345678",
|
|
DATA_MODE => C_p3_DATA_MODE,
|
|
PORT_MODE => p3_PORT_MODE
|
|
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
|
|
mcb_cmd_en_i => p3_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_i => p3_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_i => p3_mcb_cmd_bl_o_int,
|
|
mcb_wr_en_i => p3_mcb_wr_en_o_int,
|
|
|
|
vio_modify_enable => vio_modify_enable,
|
|
vio_data_mode_value => vio_data_mode_value,
|
|
vio_addr_mode_value => vio_addr_mode_value,
|
|
vio_bl_mode_value => "10",--vio_bl_mode_value,
|
|
vio_fixed_bl_value => "000000",--vio_fixed_bl_value,
|
|
|
|
mcb_init_done_i => calib_done,
|
|
cmp_error => p3_error,
|
|
run_traffic_o => p3_tg_run_traffic,
|
|
start_addr_o => p3_tg_start_addr,
|
|
end_addr_o => p3_tg_end_addr ,
|
|
cmd_seed_o => p3_tg_cmd_seed ,
|
|
data_seed_o => p3_tg_data_seed ,
|
|
load_seed_o => p3_tg_load_seed ,
|
|
addr_mode_o => p3_tg_addr_mode ,
|
|
instr_mode_o => p3_tg_instr_mode ,
|
|
bl_mode_o => p3_tg_bl_mode ,
|
|
data_mode_o => p3_tg_data_mode ,
|
|
mode_load_o => p3_tg_mode_load ,
|
|
fixed_bl_o => p3_tg_fixed_bl ,
|
|
fixed_instr_o => p3_tg_fixed_instr,
|
|
fixed_addr_o => p3_tg_fixed_addr
|
|
);
|
|
|
|
m_traffic_gen_p3 : mcb_traffic_gen
|
|
generic map(
|
|
MEM_BURST_LEN => C_MEM_BURST_LEN,
|
|
MEM_COL_WIDTH => C_MEM_NUM_COL_BITS,
|
|
NUM_DQ_PINS => C_NUM_DQ_PINS,
|
|
DQ_ERROR_WIDTH => DQ_ERROR_WIDTH,
|
|
|
|
PORT_MODE => p3_PORT_MODE,
|
|
DWIDTH => p3_DWIDTH,
|
|
CMP_DATA_PIPE_STAGES => CMP_DATA_PIPE_STAGES,
|
|
FAMILY => FAMILY,
|
|
SIMULATION => "FALSE",
|
|
DATA_PATTERN => DATA_PATTERN,
|
|
CMD_PATTERN => "CGEN_ALL",
|
|
ADDR_WIDTH => 30,
|
|
PRBS_SADDR_MASK_POS => C_p3_PRBS_SADDR_MASK_POS,
|
|
PRBS_EADDR_MASK_POS => C_p3_PRBS_EADDR_MASK_POS,
|
|
PRBS_SADDR => C_p3_BEGIN_ADDRESS,
|
|
PRBS_EADDR => C_p3_END_ADDRESS
|
|
)
|
|
port map
|
|
(
|
|
clk_i => clk0,
|
|
rst_i => rst0,
|
|
run_traffic_i => p3_tg_run_traffic,
|
|
manual_clear_error => rst0,
|
|
-- runtime parameter
|
|
start_addr_i => p3_tg_start_addr ,
|
|
end_addr_i => p3_tg_end_addr ,
|
|
cmd_seed_i => p3_tg_cmd_seed ,
|
|
data_seed_i => p3_tg_data_seed ,
|
|
load_seed_i => p3_tg_load_seed,
|
|
addr_mode_i => p3_tg_addr_mode,
|
|
|
|
instr_mode_i => p3_tg_instr_mode ,
|
|
bl_mode_i => p3_tg_bl_mode ,
|
|
data_mode_i => p3_tg_data_mode ,
|
|
mode_load_i => p3_tg_mode_load ,
|
|
|
|
-- fixed pattern inputs interface
|
|
fixed_bl_i => p3_tg_fixed_bl,
|
|
fixed_instr_i => p3_tg_fixed_instr,
|
|
fixed_addr_i => p3_tg_fixed_addr,
|
|
fixed_data_i => (others => '0'),
|
|
-- BRAM interface.
|
|
bram_cmd_i => (others => '0'),
|
|
bram_valid_i => '0',
|
|
bram_rdy_o => open,
|
|
|
|
-- MCB INTERFACE
|
|
mcb_cmd_en_o => p3_mcb_cmd_en_o_int,
|
|
mcb_cmd_instr_o => p3_mcb_cmd_instr_o_int,
|
|
mcb_cmd_bl_o => p3_mcb_cmd_bl_o_int,
|
|
mcb_cmd_addr_o => p3_mcb_cmd_addr_o_int,
|
|
mcb_cmd_full_i => p3_mcb_cmd_full_i,
|
|
|
|
mcb_wr_en_o => p3_mcb_wr_en_o_int,
|
|
mcb_wr_mask_o => p3_mcb_wr_mask_o,
|
|
mcb_wr_data_o => p3_mcb_wr_data_o,
|
|
mcb_wr_data_end_o => open,
|
|
mcb_wr_full_i => p3_mcb_wr_full_i,
|
|
mcb_wr_fifo_counts => p3_mcb_wr_fifo_counts,
|
|
|
|
mcb_rd_en_o => p3_mcb_rd_en_o,
|
|
mcb_rd_data_i => p3_mcb_rd_data_i,
|
|
mcb_rd_empty_i => p3_mcb_rd_empty_i,
|
|
mcb_rd_fifo_counts => p3_mcb_rd_fifo_counts,
|
|
|
|
-- status feedback
|
|
counts_rst => rst0,
|
|
wr_data_counts => open,
|
|
rd_data_counts => open,
|
|
cmp_data => p3_cmp_data,
|
|
cmp_data_valid => p3_cmp_data_valid,
|
|
cmp_error => p3_cmp_error,
|
|
error => p3_error,
|
|
error_status => p3_error_status,
|
|
mem_rd_data => open,
|
|
dq_error_bytelane_cmp => open,
|
|
cumlative_dq_lane_error => open
|
|
);
|
|
|
|
|
|
end architecture;
|
|
|