248 lines
8.2 KiB
VHDL
Executable File
248 lines
8.2 KiB
VHDL
Executable File
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: %version
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-- \ \ Application: MIG
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-- / / Filename: cmd_prbs_gen.vhd
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-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
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-- \ \ / \ Date Created: Jul 03 2009
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-- \___\/\___\
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--
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-- Device: Spartan6
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-- Design Name: DDR/DDR2/DDR3/LPDDR
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-- Purpose: This moduel use LFSR to generate random address, isntructions
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-- or burst_length.
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-- Reference:
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-- Revision History:
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--*****************************************************************************
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.all;
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ENTITY cmd_prbs_gen IS
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GENERIC (
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TCQ : time := 100 ps;
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FAMILY : STRING := "SPARTAN6";
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ADDR_WIDTH : INTEGER := 29;
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DWIDTH : INTEGER := 32;
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PRBS_CMD : STRING := "ADDRESS";
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PRBS_WIDTH : INTEGER := 64;
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SEED_WIDTH : INTEGER := 32;
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PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
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PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
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PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
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PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
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);
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PORT (
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clk_i : IN STD_LOGIC;
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prbs_seed_init : IN STD_LOGIC;
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clk_en : IN STD_LOGIC;
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prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
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prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
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);
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END cmd_prbs_gen;
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ARCHITECTURE trans OF cmd_prbs_gen IS
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SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
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SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
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function logb2 (val : integer) return integer is
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variable vec_con : integer;
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variable rtn : integer := 1;
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begin
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vec_con := val;
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for index in 0 to 31 loop
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if(vec_con = 1) then
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rtn := rtn + 1;
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return(rtn);
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end if;
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vec_con := vec_con/2;
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rtn := rtn + 1;
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end loop;
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end function logb2;
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BEGIN
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ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
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xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
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PROCESS (clk_i)
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BEGIN
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IF (clk_i'EVENT AND clk_i = '1') THEN
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IF (prbs_seed_init = '1') THEN
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lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
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ELSIF (clk_en = '1') THEN
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lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
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lfsr_q(63) <= lfsr_q(62) ;
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lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
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lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
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lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
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lfsr_q(1) <= lfsr_q(64) ;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (lfsr_q(32 DOWNTO 1))
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BEGIN
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prbs <= lfsr_q(32 DOWNTO 1);
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END PROCESS;
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END GENERATE;
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xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
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PROCESS (clk_i)
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BEGIN
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IF (clk_i'EVENT AND clk_i = '1') THEN
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IF (prbs_seed_init = '1') THEN
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lfsr_q <= prbs_seed_i ;
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ELSIF (clk_en = '1') THEN
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lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
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lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
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lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
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lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
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lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
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lfsr_q(2) <= lfsr_q(1) ;
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lfsr_q(1) <= lfsr_q(32) ;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (lfsr_q(32 DOWNTO 1))
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BEGIN
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IF (FAMILY = "SPARTAN6") THEN
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FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
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IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
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prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
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ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
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prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
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ELSE
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prbs(i) <= lfsr_q(i + 1);
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END IF;
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END LOOP;
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prbs(logb2(DWIDTH) downto 0) <= (others => '0');
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ELSE
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FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
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IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
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prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
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ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
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prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
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ELSE
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prbs(i) <= lfsr_q(i + 1);
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END IF;
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END LOOP;
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prbs(logb2(DWIDTH) downto 0) <= (others => '0');
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END IF;
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END PROCESS;
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END GENERATE;
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xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
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PROCESS (clk_i)
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BEGIN
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IF (clk_i'EVENT AND clk_i = '1') THEN
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IF (prbs_seed_init = '1') THEN
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lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
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ELSIF (clk_en = '1') THEN
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lfsr_q(20) <= lfsr_q(19) ;
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lfsr_q(19) <= lfsr_q(18) ;
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lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
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lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
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lfsr_q(1) <= lfsr_q(20) ;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
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BEGIN
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prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
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END PROCESS;
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END GENERATE;
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prbs_o <= prbs;
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END trans;
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