hdet/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/data_prbs_gen.vhd

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--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: %version
--  \   \         Application: MIG
--  /   /         Filename: data_prbs_gen.vhd
-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \   \  /  \    Date Created: Jul 03 2009
--  \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR 
-- Purpose:  This module is used LFSR to generate random data for memory 
--          data write or memory data read comparison.The first data is 
--          seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:

--*****************************************************************************


LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;


ENTITY data_prbs_gen IS
   GENERIC (
      EYE_TEST        : STRING := "FALSE";
      PRBS_WIDTH      : INTEGER := 32;
      SEED_WIDTH      : INTEGER := 32
--      TAPS            : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
   );
   PORT (
      
      clk_i           : IN STD_LOGIC;
      clk_en          : IN STD_LOGIC;
      rst_i           : IN STD_LOGIC;
      prbs_fseed_i    : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      prbs_seed_init  : IN STD_LOGIC;
      prbs_seed_i     : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
      
      prbs_o          : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
   );
END data_prbs_gen;

ARCHITECTURE trans OF data_prbs_gen IS
   
   SIGNAL prbs   : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
   SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
   SIGNAL i      : INTEGER;
BEGIN
   
   PROCESS (clk_i)
   BEGIN
      IF (clk_i'EVENT AND clk_i = '1') THEN
         IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
            
            
            lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
         ELSIF (clk_en = '1') THEN
            
            lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
            lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
            lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
            
            lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
            lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
            lfsr_q(2) <= lfsr_q(1);
            
            lfsr_q(1) <= lfsr_q(32);
         END IF;
      END IF;
   END PROCESS;
   
   
   PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
   BEGIN
      prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
   END PROCESS;
   
   
   prbs_o <= prbs;
   
END trans;