435 lines
16 KiB
VHDL
Executable File
435 lines
16 KiB
VHDL
Executable File
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: %version
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-- \ \ Application: MIG
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-- / / Filename: rd_data_gen.vhd
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-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
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-- \ \ / \ Date Created: Jul 03 2009
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-- \___\/\___\
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--
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-- Device: Spartan6
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-- Design Name: DDR/DDR2/DDR3/LPDDR
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-- Purpose: This module has all the timing control for generating "compare data"
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-- to compare the read data from memory.
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-- Reference:
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-- Revision History: 2010/01/09 parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
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--*****************************************************************************
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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entity rd_data_gen is
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generic (
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FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
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MEM_BURST_LEN : integer := 8;
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ADDR_WIDTH : integer := 32;
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BL_WIDTH : integer := 6;
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DWIDTH : integer := 32;
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DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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NUM_DQ_PINS : integer := 8;
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SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
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COLUMN_WIDTH : integer := 10
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);
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port (
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clk_i : in std_logic; --
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rst_i : in std_logic_vector(4 downto 0);
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prbs_fseed_i : in std_logic_vector(31 downto 0);
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data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
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rd_mdata_en : in std_logic;
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cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
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-- And then it should reasserted when
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-- it is generating the last_word.
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cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
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last_word_o : out std_logic;
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-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
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fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
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bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
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user_bl_cnt_is_1_o : out std_logic;
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data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen in sp6
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-- connect from mcb_rd_empty when used as rd_data_gen in sp6
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-- connect from rd_data_valid in v6
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-- When both data_rdy and data_valid is asserted, the ouput data is valid.
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data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
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-- pattern is available.
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data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
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);
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end entity rd_data_gen;
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ARCHITECTURE trans OF rd_data_gen IS
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COMPONENT sp6_data_gen IS
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GENERIC (
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ADDR_WIDTH : INTEGER := 32;
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BL_WIDTH : INTEGER := 6;
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DWIDTH : INTEGER := 32;
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DATA_PATTERN : STRING := "DGEN_PRBS";
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NUM_DQ_PINS : INTEGER := 8;
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COLUMN_WIDTH : INTEGER := 10
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);
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PORT (
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clk_i : IN STD_LOGIC;
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rst_i : IN STD_LOGIC;
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prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_rdy_i : IN STD_LOGIC;
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cmd_startA : IN STD_LOGIC;
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cmd_startB : IN STD_LOGIC;
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cmd_startC : IN STD_LOGIC;
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cmd_startD : IN STD_LOGIC;
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cmd_startE : IN STD_LOGIC;
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fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
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fifo_rdy_i : IN STD_LOGIC;
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data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT v6_data_gen IS
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GENERIC (
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ADDR_WIDTH : INTEGER := 32;
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MEM_BURST_LEN : integer := 8;
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BL_WIDTH : INTEGER := 6;
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DWIDTH : INTEGER := 32;
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DATA_PATTERN : STRING := "DGEN_ALL";
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NUM_DQ_PINS : INTEGER := 8;
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SEL_VICTIM_LINE : INTEGER := 3;
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COLUMN_WIDTH : INTEGER := 10
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);
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PORT (
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clk_i : IN STD_LOGIC;
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rst_i : IN STD_LOGIC;
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prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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data_rdy_i : IN STD_LOGIC;
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cmd_startA : IN STD_LOGIC;
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cmd_startB : IN STD_LOGIC;
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cmd_startC : IN STD_LOGIC;
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cmd_startD : IN STD_LOGIC;
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cmd_startE : IN STD_LOGIC;
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fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
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fifo_rdy_i : IN STD_LOGIC;
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data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
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);
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END COMPONENT;
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SIGNAL prbs_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL cmd_start : STD_LOGIC;
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SIGNAL adata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL hdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL ndata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL w1data : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL v6_w1data : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
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signal w0data : std_logic_vector(31 downto 0);
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signal data : std_logic_vector(DWIDTH - 1 downto 0);
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signal cmd_rdy : std_logic;
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signal data_valid : std_logic;
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signal user_burst_cnt : std_logic_vector(6 downto 0);
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signal data_rdy_r1 : std_logic;
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signal data_rdy_r2 : std_logic;
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signal next_count_is_one : std_logic;
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signal cmd_valid_r1 : std_logic;
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signal w3data : std_logic_vector(31 downto 0);
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signal data_port_fifo_rdy : std_logic;
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--assign cmd_start = cmd_valid_i & cmd_rdy ;
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signal user_bl_cnt_is_1 : std_logic;
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signal cmd_start_b : std_logic;
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-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
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-- counter to count user burst length
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signal u_bcount_2 : std_logic;
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-- Declare intermediate signals for referenced outputs
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signal last_word_o_xhdl1 : std_logic;
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signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
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begin
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-- Drive referenced outputs
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last_word_o <= last_word_o_xhdl1;
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data_port_fifo_rdy <= data_rdy_i;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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data_rdy_r1 <= data_rdy_i;
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data_rdy_r2 <= data_rdy_r1;
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cmd_valid_r1 <= cmd_valid_i;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
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next_count_is_one <= '1';
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else
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next_count_is_one <= '0';
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end if;
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end if;
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end process;
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user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
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(user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
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user_bl_cnt_is_1 <= '1';
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else
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user_bl_cnt_is_1 <= '0';
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end if;
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end if;
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end process;
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process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
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begin
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if (FAMILY = "SPARTAN6") then
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cmd_start <= cmd_valid_i and cmd_rdy;
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cmd_start_b <= cmd_valid_i and cmd_rdy;
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else
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if (MEM_BURST_LEN = 4) then
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cmd_start <= rd_mdata_en;
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else
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cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
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cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
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end if;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if ((rst_i(0)) = '1') then
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user_burst_cnt <= "0000000";
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elsif (cmd_start = '1') then
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if (bl_i = "000000") then
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user_burst_cnt <= "1000000" ;
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else
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user_burst_cnt <= ('0' & bl_i) ;
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end if;
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elsif (data_port_fifo_rdy = '1') then
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if (user_burst_cnt /= "0000000") then
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user_burst_cnt <= user_burst_cnt - "0000001";
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else
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user_burst_cnt <= "0000000";
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end if;
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end if;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
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u_bcount_2 <= '1';
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elsif (last_word_o_xhdl1 = '1') then
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u_bcount_2 <= '0';
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end if;
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end if;
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end process;
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last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
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-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
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-- is assert and reassert during the last data
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--data_valid_o logic
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cmd_rdy_o <= cmd_rdy;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if ((rst_i(0)) = '1') then
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cmd_rdy <= '1';
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elsif (cmd_start = '1') then
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cmd_rdy <= '0';
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elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
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cmd_rdy <= '1';
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end if;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if ((rst_i(0)) = '1') then
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data_valid <= '0';
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elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
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data_valid <= '0';
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elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
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data_valid <= '1';
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end if;
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end if;
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end process;
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process (data_valid, data_port_fifo_rdy)
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begin
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if (FAMILY = "SPARTAN6") then
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data_valid_o <= data_valid;
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else
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data_valid_o <= data_port_fifo_rdy;
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end if;
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end process;
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xhdl2 : if (FAMILY = "SPARTAN6") generate
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sp6_data_gen_inst : sp6_data_gen
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generic map (
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ADDR_WIDTH => 32,
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BL_WIDTH => BL_WIDTH,
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DWIDTH => DWIDTH,
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DATA_PATTERN => DATA_PATTERN,
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NUM_DQ_PINS => NUM_DQ_PINS,
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COLUMN_WIDTH => COLUMN_WIDTH
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i(1),
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data_rdy_i => data_rdy_i,
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prbs_fseed_i => prbs_fseed_i,
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data_mode_i => data_mode_i,
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cmd_startA => cmd_start,
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cmd_startB => cmd_start,
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cmd_startC => cmd_start,
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cmd_startD => cmd_start,
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cmd_startE => cmd_start,
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fixed_data_i => fixed_data_i,
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addr_i => addr_i,
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user_burst_cnt => user_burst_cnt,
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fifo_rdy_i => data_port_fifo_rdy,
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data_o => data_o
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);
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end generate;
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xhdl3 : if (FAMILY = "VIRTEX6") generate
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v6_data_gen_inst : v6_data_gen
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generic map (
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ADDR_WIDTH => 32,
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BL_WIDTH => BL_WIDTH,
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MEM_BURST_LEN => MEM_BURST_LEN,
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DWIDTH => DWIDTH,
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DATA_PATTERN => DATA_PATTERN,
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NUM_DQ_PINS => NUM_DQ_PINS,
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SEL_VICTIM_LINE => SEL_VICTIM_LINE,
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COLUMN_WIDTH => COLUMN_WIDTH
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i(1),
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data_rdy_i => data_rdy_i,
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prbs_fseed_i => prbs_fseed_i,
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data_mode_i => data_mode_i,
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cmd_startA => cmd_start,
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cmd_startB => cmd_start,
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cmd_startC => cmd_start,
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cmd_startD => cmd_start,
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cmd_startE => cmd_start,
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fixed_data_i => fixed_data_i,
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m_addr_i => addr_i, --(m_addr_i ),
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addr_i => addr_i,
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user_burst_cnt => user_burst_cnt,
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fifo_rdy_i => data_port_fifo_rdy,
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data_o => data_o
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);
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end generate;
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end architecture trans;
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