639 lines
24 KiB
VHDL
Executable File
639 lines
24 KiB
VHDL
Executable File
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: %version
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-- \ \ Application: MIG
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-- / / Filename: read_data_path.vhd
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-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
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-- \ \ / \ Date Created: Jul 03 2009
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-- \___\/\___\
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--
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-- Device: Spartan6
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-- Design Name: DDR/DDR2/DDR3/LPDDR
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-- Purpose: This is top level of read path and also consist of comparison logic
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-- for read data.
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-- Reference:
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-- Revision History:
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--*****************************************************************************
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.all;
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entity read_data_path is
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generic (
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TCQ : time := 100 ps;
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FAMILY : string := "VIRTEX6";
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MEM_BURST_LEN : integer := 8;
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ADDR_WIDTH : integer := 32;
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CMP_DATA_PIPE_STAGES : integer := 3;
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DWIDTH : integer := 32;
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DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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NUM_DQ_PINS : integer := 8;
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DQ_ERROR_WIDTH : integer := 1;
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SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
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MEM_COL_WIDTH : integer := 10
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);
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port (
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clk_i : in std_logic;
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manual_clear_error : in std_logic;
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rst_i : in std_logic_vector(9 downto 0);
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cmd_rdy_o : out std_logic;
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cmd_valid_i : in std_logic;
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prbs_fseed_i : in std_logic_vector(31 downto 0);
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data_mode_i : in std_logic_vector(3 downto 0);
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cmd_sent : in std_logic_vector(2 downto 0);
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bl_sent : in std_logic_vector(5 downto 0);
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cmd_en_i : in std_logic;
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-- m_addr_i : in std_logic_vector(31 downto 0);
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fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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addr_i : in std_logic_vector(31 downto 0);
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bl_i : in std_logic_vector(5 downto 0);
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-- input [5:0] port_data_counts_i,// connect to data port fifo counts
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data_rdy_o : out std_logic;
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data_valid_i : in std_logic;
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data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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last_word_rd_o : out std_logic;
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data_error_o : out std_logic;
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cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
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rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
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cmp_data_valid : out std_logic;
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cmp_addr_o : out std_logic_vector(31 downto 0);
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cmp_bl_o : out std_logic_vector(5 downto 0);
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force_wrcmd_gen_o : out std_logic;
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rd_buff_avail_o : out std_logic_vector(6 downto 0);
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dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
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cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
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);
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end entity read_data_path;
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architecture trans of read_data_path is
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function REDUCTION_OR( A: in std_logic_vector) return std_logic is
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variable tmp : std_logic := '0';
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begin
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for i in A'range loop
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tmp := tmp or A(i);
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end loop;
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return tmp;
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end function REDUCTION_OR;
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COMPONENT read_posted_fifo IS
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GENERIC (
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TCQ : time := 100 ps;
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MEM_BURST_LEN : integer := 4;
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FAMILY : STRING := "SPARTAN6";
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ADDR_WIDTH : INTEGER := 32;
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BL_WIDTH : INTEGER := 6
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);
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PORT (
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clk_i : IN STD_LOGIC;
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rst_i : IN STD_LOGIC;
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cmd_rdy_o : OUT STD_LOGIC;
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cmd_valid_i : IN STD_LOGIC;
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data_valid_i : IN STD_LOGIC;
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addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
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user_bl_cnt_is_1 : IN STD_LOGIC;
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cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
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bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
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cmd_en_i : IN STD_LOGIC;
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gen_rdy_i : IN STD_LOGIC;
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gen_valid_o : OUT STD_LOGIC;
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gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
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rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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rd_mdata_fifo_empty : IN STD_LOGIC;
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rd_mdata_en : OUT STD_LOGIC
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);
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END COMPONENT;
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component rd_data_gen is
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generic (
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FAMILY : string := "SPARTAN6";
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MEM_BURST_LEN : integer := 8;
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ADDR_WIDTH : integer := 32;
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BL_WIDTH : integer := 6;
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DWIDTH : integer := 32;
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DATA_PATTERN : string := "DGEN_PRBS";
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NUM_DQ_PINS : integer := 8;
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SEL_VICTIM_LINE : integer := 3;
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COLUMN_WIDTH : integer := 10
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic_vector(4 downto 0);
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prbs_fseed_i : in std_logic_vector(31 downto 0);
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rd_mdata_en : in std_logic;
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data_mode_i : in std_logic_vector(3 downto 0);
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cmd_rdy_o : out std_logic;
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cmd_valid_i : in std_logic;
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last_word_o : out std_logic;
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-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
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addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
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bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
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user_bl_cnt_is_1_o : out std_logic;
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data_rdy_i : in std_logic;
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data_valid_o : out std_logic;
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data_o : out std_logic_vector(DWIDTH - 1 downto 0)
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);
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end component;
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component afifo IS
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GENERIC (
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DSIZE : INTEGER := 32;
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FIFO_DEPTH : INTEGER := 16;
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ASIZE : INTEGER := 5;
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SYNC : INTEGER := 1
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);
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PORT (
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wr_clk : IN STD_LOGIC;
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rst : IN STD_LOGIC;
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wr_en : IN STD_LOGIC;
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wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
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rd_en : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
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almost_full : OUT STD_LOGIC;
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full : OUT STD_LOGIC;
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empty : OUT STD_LOGIC
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);
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END component;
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signal gen_rdy : std_logic;
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signal gen_valid : std_logic;
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signal gen_addr : std_logic_vector(31 downto 0);
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signal gen_bl : std_logic_vector(5 downto 0);
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signal cmp_rdy : std_logic;
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signal cmp_valid : std_logic;
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signal cmp_addr : std_logic_vector(31 downto 0);
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signal cmp_bl : std_logic_vector(5 downto 0);
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signal data_error : std_logic;
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signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
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signal last_word_rd : std_logic;
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signal bl_counter : std_logic_vector(5 downto 0);
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signal cmd_rdy : std_logic;
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signal user_bl_cnt_is_1 : std_logic;
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signal data_rdy : std_logic;
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signal delayed_data : std_logic_vector(DWIDTH downto 0);
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-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
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signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
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signal rd_mdata_en : std_logic;
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signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
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signal force_wrcmd_gen : std_logic;
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signal wait_bl_end : std_logic;
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signal wait_bl_end_r1 : std_logic;
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signal v6_data_cmp_valid : std_logic;
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signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
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signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
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signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
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signal l_data_error : std_logic;
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signal u_data_error : std_logic;
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signal cmp_data_en : std_logic;
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signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
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signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
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signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
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signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
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signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
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signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
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signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
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signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
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signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
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signal rd_mdata_fifo_empty : std_logic;
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signal data_valid_r : std_logic;
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-- Declare intermediate signals for referenced outputs
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-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
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-- SIGNAL tmp_sig : STD_LOGIC;
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signal last_word_rd_o_xhdl0 : std_logic;
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signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
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begin
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-- Drive referenced outputs
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last_word_rd_o <= last_word_rd_o_xhdl0;
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rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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wait_bl_end_r1 <= wait_bl_end;
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rd_data_r <= data_i;
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end if;
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end process;
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force_wrcmd_gen_o <= force_wrcmd_gen;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if (rst_i(0) = '1') then
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force_wrcmd_gen <= '0';
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elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
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force_wrcmd_gen <= '0';
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elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
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force_wrcmd_gen <= '1';
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end if;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if (rst_i(0) = '1') then
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force_wrcmd_timeout_cnts <= "00000000";
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elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
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force_wrcmd_timeout_cnts <= "00000000";
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elsif (force_wrcmd_gen = '1') then
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force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
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end if;
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end if;
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end process;
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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if (rst_i(0) = '1') then
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wait_bl_end <= '0';
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elsif (force_wrcmd_timeout_cnts = "11111111") then
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wait_bl_end <= '0';
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elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
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wait_bl_end <= '1';
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elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
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wait_bl_end <= '0';
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end if;
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end if;
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end process;
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cmd_rdy_o <= cmd_rdy;
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read_postedfifo : read_posted_fifo
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GENERIC MAP (
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TCQ => TCQ,
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FAMILY => FAMILY,
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MEM_BURST_LEN => MEM_BURST_LEN,
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ADDR_WIDTH => 32,
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BL_WIDTH => 6
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i(0),
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cmd_rdy_o => cmd_rdy,
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cmd_valid_i => cmd_valid_i,
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data_valid_i => data_rdy,
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addr_i => addr_i,
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bl_i => bl_i,
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cmd_sent => cmd_sent,
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bl_sent => bl_sent,
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cmd_en_i => cmd_en_i,
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user_bl_cnt_is_1 => user_bl_cnt_is_1,
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gen_rdy_i => gen_rdy,
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gen_valid_o => gen_valid,
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gen_addr_o => gen_addr,
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gen_bl_o => gen_bl,
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rd_buff_avail_o => rd_buff_avail_o_xhdl1,
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rd_mdata_fifo_empty => rd_mdata_fifo_empty,
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rd_mdata_en => rd_mdata_en
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);
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rd_datagen : rd_data_gen
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generic map (
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FAMILY => FAMILY,
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MEM_BURST_LEN => MEM_BURST_LEN,
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NUM_DQ_PINS => NUM_DQ_PINS,
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SEL_VICTIM_LINE => SEL_VICTIM_LINE,
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DATA_PATTERN => DATA_PATTERN,
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DWIDTH => DWIDTH,
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COLUMN_WIDTH => MEM_COL_WIDTH
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i(4 downto 0),
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prbs_fseed_i => prbs_fseed_i,
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data_mode_i => data_mode_i,
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cmd_rdy_o => gen_rdy,
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cmd_valid_i => gen_valid,
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last_word_o => last_word_rd_o_xhdl0,
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-- m_addr_i => m_addr_i,
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fixed_data_i => fixed_data_i,
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addr_i => gen_addr,
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bl_i => gen_bl,
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user_bl_cnt_is_1_o => user_bl_cnt_is_1,
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data_rdy_i => data_valid_i,
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data_valid_o => cmp_valid,
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data_o => cmp_data,
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rd_mdata_en => rd_mdata_en
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);
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rd_mdata_fifo : afifo
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GENERIC MAP (
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DSIZE => DWIDTH,
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FIFO_DEPTH => 32,
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ASIZE => 5,
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SYNC => 1
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)
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PORT MAP (
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wr_clk => clk_i,
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rst => rst_i(0),
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wr_en => data_valid_i,
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wr_data => data_i,
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rd_en => rd_mdata_en,
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rd_clk => clk_i,
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rd_data => rd_v6_mdata,
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full => open,
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empty => rd_mdata_fifo_empty,
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almost_full => open
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);
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-- tmp_sig <= cmp_valid AND data_valid_i;
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-- xhdl2 <= ( tmp_sig & cmp_data);
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process (clk_i)
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begin
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if (clk_i'event and clk_i = '1') then
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-- delayed_data <= (tmp_sig & cmp_data);
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cmp_data_r <= cmp_data;
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end if;
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end process;
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rd_mdata_o <= rd_mdata;
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rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
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WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
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cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
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WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
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cmp_data_o <= cmp_data_r;
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cmp_addr_o <= gen_addr;
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cmp_bl_o <= gen_bl;
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-- xhdl4 : if (FAMILY = "SPARTAN6") generate
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-- rd_data_o <= rd_data_r;
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-- end generate;
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|
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
|
|
-- rd_data_o <= data_i;
|
|
-- end generate;
|
|
|
|
data_rdy_o <= data_rdy;
|
|
data_rdy <= cmp_valid and data_valid_i;
|
|
|
|
process (clk_i)
|
|
begin
|
|
if (clk_i'event and clk_i = '1') then
|
|
v6_data_cmp_valid <= rd_mdata_en;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
process (clk_i)
|
|
begin
|
|
if (clk_i'event and clk_i = '1') then
|
|
cmp_data_en <= data_rdy;
|
|
end if;
|
|
end process;
|
|
|
|
xhdl6 : if (FAMILY = "SPARTAN6") generate
|
|
process (clk_i)
|
|
begin
|
|
if (clk_i'event and clk_i = '1') then
|
|
if (cmp_data_en = '1') then
|
|
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
|
|
l_data_error <= '1' ;
|
|
ELSE
|
|
l_data_error <= '0' ;
|
|
END IF;
|
|
else
|
|
l_data_error <= '0' ;
|
|
end if;
|
|
if (cmp_data_en = '1') then
|
|
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
|
|
u_data_error <= '1' ;
|
|
ELSE
|
|
u_data_error <= '0' ;
|
|
END IF;
|
|
else
|
|
u_data_error <= '0' ;
|
|
end if;
|
|
data_error <= l_data_error or u_data_error;
|
|
--synthesis translate_off
|
|
if (data_error = '1') then
|
|
report ("DATA ERROR");
|
|
end if;
|
|
--synthesis translate_on
|
|
|
|
end if;
|
|
end process;
|
|
|
|
end generate;
|
|
|
|
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
|
|
|
|
|
|
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
|
|
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
|
|
|
|
end generate;
|
|
process (clk_i)
|
|
begin
|
|
if (clk_i'event and clk_i = '1') then
|
|
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
|
|
error_byte_r1 <= (others => '0');
|
|
data_error <= '0';
|
|
ELSE
|
|
|
|
error_byte_r1 <= error_byte;
|
|
-- FOR i IN 0 TO DWIDTH - 1 LOOP
|
|
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
|
|
-- END LOOP;
|
|
|
|
|
|
END IF;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
process (data_error)
|
|
begin
|
|
|
|
--synthesis translate_off
|
|
IF (data_error = '1') THEN
|
|
|
|
report "DATA ERROR"; -- severity ERROR;
|
|
END IF;
|
|
--synthesis translate_on
|
|
end process;
|
|
|
|
|
|
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
|
|
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
|
|
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
|
|
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
|
|
|
|
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
|
|
end generate;
|
|
|
|
|
|
process (clk_i)
|
|
begin
|
|
IF (clk_i'event and clk_i = '1') then
|
|
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
|
|
|
|
dq_lane_error_r1 <= (others => '0');
|
|
dq_lane_error_r2 <= (others => '0');
|
|
data_valid_r <= '0';
|
|
cumlative_dq_lane_error_reg <= (others => '0');
|
|
|
|
ELSE
|
|
data_valid_r <= data_valid_i;
|
|
|
|
dq_lane_error_r1 <= dq_lane_error;
|
|
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
|
|
END IF;
|
|
|
|
|
|
END IF;
|
|
end process;
|
|
|
|
|
|
|
|
end generate;
|
|
|
|
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
|
|
|
|
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
|
|
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
|
|
end generate;
|
|
|
|
process (clk_i)
|
|
begin
|
|
if (clk_i'event and clk_i = '1') then
|
|
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
|
|
error_byte_r1 <= (others => '0');
|
|
data_error <= '0';
|
|
ELSE
|
|
|
|
error_byte_r1 <= error_byte;
|
|
--FOR i IN 0 TO DWIDTH - 1 LOOP
|
|
-- data_error <= error_byte_r1(i) OR data_error;
|
|
--END LOOP;
|
|
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
|
|
|
|
--synthesis translate_off
|
|
IF (data_error = '1') THEN
|
|
|
|
report "DATA ERROR"; -- severity ERROR;
|
|
end if;
|
|
--synthesis translate_on
|
|
END IF;
|
|
end if;
|
|
end process;
|
|
|
|
|
|
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
|
|
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
|
|
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
|
|
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
|
|
|
|
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
|
|
end generate;
|
|
|
|
process (clk_i)
|
|
begin
|
|
IF (clk_i'event and clk_i = '1') then
|
|
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
|
|
|
|
dq_lane_error_r1 <= (others => '0');
|
|
dq_lane_error_r2 <= (others => '0');
|
|
data_valid_r <= '0';
|
|
cumlative_dq_lane_error_reg <= (others => '0');
|
|
|
|
ELSE
|
|
data_valid_r <= data_valid_i;
|
|
|
|
dq_lane_error_r1 <= dq_lane_error;
|
|
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
|
|
END IF;
|
|
|
|
|
|
END IF;
|
|
end process;
|
|
|
|
end generate;
|
|
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
|
|
|
|
dq_error_bytelane_cmp <= dq_lane_error_r1;
|
|
|
|
data_error_o <= data_error;
|
|
|
|
end architecture trans;
|
|
|
|
|
|
|
|
|