hdet/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/tg_status.vhd

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--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: %version
--  \   \         Application: MIG
--  /   /         Filename: tg_status.vhd
-- /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \   \  /  \    Date Created: Jul 03 2009
--  \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR 
-- Purpose:  This module compare the memory read data agaisnt compare data that generated from data_gen module.
--          Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:

--*****************************************************************************

LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;

entity tg_status is
   generic (
      TCQ             : TIME   := 100 ps;
      DWIDTH                         : integer := 32
   );
   port (
      
      clk_i                          : in std_logic;
      rst_i                          : in std_logic;
      manual_clear_error             : in std_logic;
      data_error_i                   : in std_logic;
      cmp_data_i                     : in std_logic_vector(DWIDTH - 1 downto 0);
      rd_data_i                      : in std_logic_vector(DWIDTH - 1 downto 0);
      cmp_addr_i                     : in std_logic_vector(31 downto 0);
      cmp_bl_i                       : in std_logic_vector(5 downto 0);
      mcb_cmd_full_i                 : in std_logic;
      mcb_wr_full_i                  : in std_logic;
      mcb_rd_empty_i                 : in std_logic;
      error_status                   : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
      error                          : out std_logic
   );
end entity tg_status;

architecture trans of tg_status is
   
   signal data_error_r             : std_logic;
   signal error_set                : std_logic;
begin
   error <= error_set;
   
   process (clk_i)
   begin
      if (clk_i'event and clk_i = '1') then
         
         data_error_r <= data_error_i;
      end if;
   end process;
   
   process (clk_i)
   begin
      if (clk_i'event and clk_i = '1') then
         
         if ((rst_i or manual_clear_error) = '1') then
--            error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
              error_status <= (others => '0');
            error_set <= '0';
         else
            -- latch the first error only
            if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
               error_status(31 downto 0) <= cmp_addr_i;
               error_status(37 downto 32) <= cmp_bl_i;
               error_status(40) <= mcb_cmd_full_i;
               error_status(41) <= mcb_wr_full_i;
               error_status(42) <= mcb_rd_empty_i;
               error_set <= '1';
               error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
               
               error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
            end if;
            
            error_status(39 downto 38) <= "00";		-- reserved
            
            error_status(63 downto 43) <= "000000000000000000000";		-- reserved
         end if;
      end if;
   end process;
   
   
end architecture trans;