211 lines
8.9 KiB
VHDL
Executable File
211 lines
8.9 KiB
VHDL
Executable File
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version: %version
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-- \ \ Application: MIG
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-- / / Filename: write_data_path.vhd
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-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
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-- \ \ / \ Date Created: Jul 03 2009
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-- \___\/\___\
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--
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-- Device: Spartan6
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-- Design Name: DDR/DDR2/DDR3/LPDDR
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-- Purpose: This is top level of write path.
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-- Reference:
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-- Revision History:
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--*****************************************************************************
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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entity write_data_path is
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generic (
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TCQ : TIME := 100 ps;
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MEM_BURST_LEN : integer := 8;
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FAMILY : string := "SPARTAN6";
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ADDR_WIDTH : integer := 32;
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DWIDTH : integer := 32;
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DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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NUM_DQ_PINS : integer := 8;
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SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
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MEM_COL_WIDTH : integer := 10;
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EYE_TEST : string := "FALSE"
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);
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port (
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clk_i : in std_logic;
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rst_i : in std_logic_vector(9 downto 0);
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cmd_rdy_o : out std_logic;
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cmd_valid_i : in std_logic;
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cmd_validB_i : in std_logic;
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cmd_validC_i : in std_logic;
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prbs_fseed_i : in std_logic_vector(31 downto 0);
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data_mode_i : in std_logic_vector(3 downto 0);
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-- m_addr_i : in std_logic_vector(31 downto 0);
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fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
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addr_i : in std_logic_vector(31 downto 0);
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bl_i : in std_logic_vector(5 downto 0);
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-- input [5:0] port_data_counts_i,// connect to data port fifo counts
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data_rdy_i : in std_logic;
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data_valid_o : out std_logic;
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last_word_wr_o : out std_logic;
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data_o : out std_logic_vector(DWIDTH - 1 downto 0);
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data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
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data_wr_end_o : out std_logic );
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end entity write_data_path;
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architecture trans of write_data_path is
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COMPONENT wr_data_gen IS
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GENERIC (
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TCQ : TIME := 100 ps;
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FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
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MODE : STRING := "WR"; --"WR", "RD"
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MEM_BURST_LEN : integer := 8;
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ADDR_WIDTH : INTEGER := 32;
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BL_WIDTH : INTEGER := 6;
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DWIDTH : INTEGER := 32;
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DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
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NUM_DQ_PINS : INTEGER := 8;
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SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
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COLUMN_WIDTH : INTEGER := 10;
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EYE_TEST : STRING := "FALSE"
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);
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PORT (
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clk_i : IN STD_LOGIC;
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rst_i : in STD_LOGIC_VECTOR(4 downto 0);
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prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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cmd_rdy_o : OUT STD_LOGIC;
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cmd_valid_i : IN STD_LOGIC;
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cmd_validB_i : IN STD_LOGIC;
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cmd_validC_i : IN STD_LOGIC;
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last_word_o : OUT STD_LOGIC;
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fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
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-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
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bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
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data_rdy_i : IN STD_LOGIC;
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data_valid_o : OUT STD_LOGIC;
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data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
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data_wr_end_o : OUT STD_LOGIC
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);
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END COMPONENT;
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signal data_valid : std_logic;
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signal cmd_rdy : std_logic;
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-- Declare intermediate signals for referenced outputs
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signal cmd_rdy_o_xhdl0 : std_logic;
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signal last_word_wr_o_xhdl3 : std_logic;
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signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
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signal data_wr_end_o_xhdl2 : std_logic;
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begin
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-- Drive referenced outputs
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cmd_rdy_o <= cmd_rdy_o_xhdl0;
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last_word_wr_o <= last_word_wr_o_xhdl3;
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data_o <= data_o_xhdl1;
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data_wr_end_o <= data_wr_end_o_xhdl2;
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data_valid_o <= data_valid and data_rdy_i;
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-- data_mask_o <= "0000"; -- for now
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data_mask_o <= (others => '0');
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wr_data_gen_inst : wr_data_gen
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generic map (
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TCQ => TCQ,
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family => FAMILY,
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num_dq_pins => NUM_DQ_PINS,
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sel_victim_line => SEL_VICTIM_LINE,
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MEM_BURST_LEN => MEM_BURST_LEN,
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data_pattern => DATA_PATTERN,
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dwidth => DWIDTH,
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column_width => MEM_COL_WIDTH,
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eye_test => EYE_TEST
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)
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port map (
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clk_i => clk_i,
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rst_i => rst_i(9 downto 5),
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prbs_fseed_i => prbs_fseed_i,
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data_mode_i => data_mode_i,
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cmd_rdy_o => cmd_rdy_o_xhdl0,
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cmd_valid_i => cmd_valid_i,
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cmd_validb_i => cmd_validB_i,
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cmd_validc_i => cmd_validC_i,
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last_word_o => last_word_wr_o_xhdl3,
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-- .port_data_counts_i (port_data_counts_i),
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-- m_addr_i => m_addr_i,
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fixed_data_i => fixed_data_i,
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addr_i => addr_i,
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bl_i => bl_i,
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data_rdy_i => data_rdy_i,
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data_valid_o => data_valid,
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data_o => data_o_xhdl1,
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data_wr_end_o => data_wr_end_o_xhdl2
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);
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end architecture trans;
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