446 lines
16 KiB
VHDL
446 lines
16 KiB
VHDL
--*****************************************************************************
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-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.92
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-- \ \ Application : MIG
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-- / / Filename : sim_tb_top.vhd
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-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
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-- \ \ / \ Date Created : Jul 03 2009
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-- \___\/\___\
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--
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-- Device : Spartan-6
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-- Design Name : DDR/DDR2/DDR3/LPDDR
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-- Purpose : This is the simulation testbench which is used to verify the
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-- design. The basic clocks and resets to the interface are
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-- generated here. This also connects the memory interface to the
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-- memory model.
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--*****************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library unisim;
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use unisim.vcomponents.all;
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entity sim_tb_top is
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end entity sim_tb_top;
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architecture arch of sim_tb_top is
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-- ========================================================================== --
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-- Parameters --
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-- ========================================================================== --
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constant DEBUG_EN : integer :=0;
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constant C3_HW_TESTING : string := "FALSE";
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function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
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begin
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if (C3_HW_TESTING = "FALSE") then
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return val1;
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else
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return val2;
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end if;
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end function;
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constant C3_MEMCLK_PERIOD : integer := 3000;
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constant C3_RST_ACT_LOW : integer := 0;
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constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
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constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
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constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
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constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
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constant C3_NUM_DQ_PINS : integer := 16;
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constant C3_MEM_ADDR_WIDTH : integer := 13;
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constant C3_MEM_BANKADDR_WIDTH : integer := 3;
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constant C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
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constant C3_P0_MASK_SIZE : integer := 4;
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constant C3_P0_DATA_PORT_SIZE : integer := 32;
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constant C3_P1_MASK_SIZE : integer := 4;
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constant C3_P1_DATA_PORT_SIZE : integer := 32;
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constant C3_CALIB_SOFT_IP : string := "TRUE";
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constant C3_SIMULATION : string := "TRUE";
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-- ========================================================================== --
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-- Component Declarations
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-- ========================================================================== --
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component example_top is
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generic
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(
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C3_P0_MASK_SIZE : integer;
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C3_P0_DATA_PORT_SIZE : integer;
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C3_P1_MASK_SIZE : integer;
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C3_P1_DATA_PORT_SIZE : integer;
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C3_MEMCLK_PERIOD : integer;
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C3_RST_ACT_LOW : integer;
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C3_INPUT_CLK_TYPE : string;
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DEBUG_EN : integer;
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C3_CALIB_SOFT_IP : string;
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C3_SIMULATION : string;
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C3_HW_TESTING : string;
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C3_MEM_ADDR_ORDER : string;
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C3_NUM_DQ_PINS : integer;
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C3_MEM_ADDR_WIDTH : integer;
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C3_MEM_BANKADDR_WIDTH : integer
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);
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port
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(
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calib_done : out std_logic;
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error : out std_logic;
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mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
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mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
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mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
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mcb3_dram_ras_n : out std_logic;
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mcb3_dram_cas_n : out std_logic;
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mcb3_dram_we_n : out std_logic;
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mcb3_dram_odt : out std_logic;
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mcb3_dram_cke : out std_logic;
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mcb3_dram_dm : out std_logic;
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mcb3_rzq : inout std_logic;
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mcb3_zio : inout std_logic;
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c3_sys_clk : in std_logic;
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c3_sys_rst_i : in std_logic;
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mcb3_dram_dqs : inout std_logic;
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mcb3_dram_dqs_n : inout std_logic;
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mcb3_dram_udqs : inout std_logic;
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mcb3_dram_udqs_n : inout std_logic;
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mcb3_dram_udm : out std_logic;
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mcb3_dram_ck : out std_logic;
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mcb3_dram_ck_n : out std_logic
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);
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end component;
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component ddr2_model_c3 is
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port (
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ck : in std_logic;
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ck_n : in std_logic;
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cke : in std_logic;
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cs_n : in std_logic;
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ras_n : in std_logic;
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cas_n : in std_logic;
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we_n : in std_logic;
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dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
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ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
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addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
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dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
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dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
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dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
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rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
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odt : in std_logic
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);
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end component;
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-- ========================================================================== --
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-- Signal Declarations --
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-- ========================================================================== --
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-- Clocks
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signal c3_sys_clk : std_logic := '0';
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signal c3_sys_clk_p : std_logic;
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signal c3_sys_clk_n : std_logic;
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-- System Reset
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signal c3_sys_rst : std_logic := '0';
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signal c3_sys_rst_i : std_logic;
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-- Design-Top Port Map
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signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
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signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
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signal mcb3_dram_ck : std_logic;
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signal mcb3_dram_ck_n : std_logic;
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signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
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signal mcb3_dram_dqs : std_logic;
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signal mcb3_dram_dqs_n : std_logic;
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signal mcb3_dram_dm : std_logic;
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signal mcb3_dram_ras_n : std_logic;
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signal mcb3_dram_cas_n : std_logic;
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signal mcb3_dram_we_n : std_logic;
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signal mcb3_dram_cke : std_logic;
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signal mcb3_dram_odt : std_logic;
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signal calib_done : std_logic;
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signal error : std_logic;
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signal mcb3_dram_udqs : std_logic;
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signal mcb3_dram_udqs_n : std_logic;
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signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
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signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
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signal mcb3_dram_udm :std_logic; -- for X16 parts
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signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
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signal mcb3_command : std_logic_vector(2 downto 0);
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signal mcb3_enable1 : std_logic;
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signal mcb3_enable2 : std_logic;
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signal rzq3 : std_logic;
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signal zio3 : std_logic;
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function vector (asi:std_logic) return std_logic_vector is
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variable v : std_logic_vector(0 downto 0) ;
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begin
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v(0) := asi;
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return(v);
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end function vector;
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begin
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-- ========================================================================== --
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-- Clocks Generation --
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-- ========================================================================== --
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process
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begin
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c3_sys_clk <= not c3_sys_clk;
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wait for (C3_TCYC_SYS_DIV2);
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end process;
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c3_sys_clk_p <= c3_sys_clk;
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c3_sys_clk_n <= not c3_sys_clk;
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-- ========================================================================== --
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-- Reset Generation --
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-- ========================================================================== --
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process
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begin
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c3_sys_rst <= '0';
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wait for 200 ns;
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c3_sys_rst <= '1';
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wait;
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end process;
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c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
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-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
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-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
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zio_pulldown3 : PULLDOWN port map(O => zio3);
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rzq_pulldown3 : PULLDOWN port map(O => rzq3);
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-- ========================================================================== --
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-- DESIGN TOP INSTANTIATION --
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-- ========================================================================== --
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design_top : example_top generic map
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(
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C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
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C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
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C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
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C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
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C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
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C3_RST_ACT_LOW => C3_RST_ACT_LOW,
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C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
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DEBUG_EN => DEBUG_EN,
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C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
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C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
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C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
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C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
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C3_HW_TESTING => C3_HW_TESTING,
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C3_SIMULATION => C3_SIMULATION,
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C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
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)
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port map (
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calib_done => calib_done,
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error => error,
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c3_sys_clk => c3_sys_clk,
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c3_sys_rst_i => c3_sys_rst_i,
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mcb3_dram_dq => mcb3_dram_dq,
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mcb3_dram_a => mcb3_dram_a,
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mcb3_dram_ba => mcb3_dram_ba,
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mcb3_dram_ras_n => mcb3_dram_ras_n,
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mcb3_dram_cas_n => mcb3_dram_cas_n,
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mcb3_dram_we_n => mcb3_dram_we_n,
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mcb3_dram_odt => mcb3_dram_odt,
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mcb3_dram_cke => mcb3_dram_cke,
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mcb3_dram_ck => mcb3_dram_ck,
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mcb3_dram_ck_n => mcb3_dram_ck_n,
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mcb3_dram_dqs_n => mcb3_dram_dqs_n,
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mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
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mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
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mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
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mcb3_dram_dm => mcb3_dram_dm,
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mcb3_rzq => rzq3,
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mcb3_zio => zio3,
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mcb3_dram_dqs => mcb3_dram_dqs
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);
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-- ========================================================================== --
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-- Memory model instances --
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-- ========================================================================== --
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mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
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process(mcb3_dram_ck)
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begin
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if (rising_edge(mcb3_dram_ck)) then
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if (c3_sys_rst = '0') then
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mcb3_enable1 <= '0';
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mcb3_enable2 <= '0';
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elsif (mcb3_command = "100") then
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mcb3_enable2 <= '0';
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elsif (mcb3_command = "101") then
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mcb3_enable2 <= '1';
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else
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mcb3_enable2 <= mcb3_enable2;
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end if;
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mcb3_enable1 <= mcb3_enable2;
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end if;
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end process;
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-----------------------------------------------------------------------------
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--read
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-----------------------------------------------------------------------------
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mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
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when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
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else "ZZ";
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mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
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when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
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else "ZZ";
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-----------------------------------------------------------------------------
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--write
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-----------------------------------------------------------------------------
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mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
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when ( mcb3_enable1 = '1') else 'Z';
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mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
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when (mcb3_enable1 = '1') else 'Z';
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mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
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when (mcb3_enable1 = '1') else 'Z';
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mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
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when (mcb3_enable1 = '1') else 'Z';
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mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
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u_mem_c3 : ddr2_model_c3 port map(
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ck => mcb3_dram_ck,
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ck_n => mcb3_dram_ck_n,
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cke => mcb3_dram_cke,
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cs_n => '0',
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ras_n => mcb3_dram_ras_n,
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cas_n => mcb3_dram_cas_n,
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we_n => mcb3_dram_we_n,
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dm_rdqs => mcb3_dram_dm_vector ,
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ba => mcb3_dram_ba,
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addr => mcb3_dram_a,
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dq => mcb3_dram_dq,
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dqs => mcb3_dram_dqs_vector,
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dqs_n => mcb3_dram_dqs_n_vector,
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rdqs_n => open,
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odt => mcb3_dram_odt
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);
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-----------------------------------------------------------------------------
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-- Reporting the test case status
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-----------------------------------------------------------------------------
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Logging: process
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begin
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wait for 200 us;
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if (calib_done = '1') then
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if (error = '0') then
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report ("****TEST PASSED****");
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else
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report ("****TEST FAILED: DATA ERROR****");
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end if;
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else
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report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
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end if;
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end process;
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end architecture;
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