hdet/fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc

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2.0 KiB
Tcl

# Synplicity, Inc. constraint file
# Written on Mon Jun 27 15:50:39 2005
define_attribute {v:work.example_top} syn_hier {hard}
define_attribute {v:work.iodrp_controller} syn_hier {hard}
define_attribute {v:work.iodrp_mcb_controller} syn_hier {hard}
define_attribute {v:work.mcb_raw_wrapper} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration_top} syn_hier {hard}
define_attribute {v:work.memc3_infrastructure} syn_hier {hard}
define_attribute {v:work.memc3_tb_top} syn_hier {hard}
define_attribute {v:work.memc3_wrapper} syn_hier {hard}
define_attribute {v:work.afifo} syn_hier {hard}
define_attribute {v:work.cmd_gen} syn_hier {hard}
define_attribute {v:work.cmd_prbs_gen} syn_hier {hard}
define_attribute {v:work.data_prbs_gen} syn_hier {hard}
define_attribute {v:work.init_mem_pattern_ctr} syn_hier {hard}
define_attribute {v:work.mcb_flow_control} syn_hier {hard}
define_attribute {v:work.mcb_traffic_gen} syn_hier {hard}
define_attribute {v:work.rd_data_gen} syn_hier {hard}
define_attribute {v:work.read_data_path} syn_hier {hard}
define_attribute {v:work.read_posted_fifo} syn_hier {hard}
define_attribute {v:work.sp6_data_gen} syn_hier {hard}
define_attribute {v:work.tg_status} syn_hier {hard}
define_attribute {v:work.v6_data_gen} syn_hier {hard}
define_attribute {v:work.wr_data_gen} syn_hier {hard}
define_attribute {v:work.write_data_path} syn_hier {hard}
# clock Constraints
define_clock -disable -name {memc3_infrastructure_inst} -period 3000 -clockgroup default_clkgroup_1
define_clock -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3000 -clockgroup default_clkgroup_2
define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3000 -clockgroup default_clkgroup_3