49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 11.1
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# Date: Wed Mar 11 07:09:11 2009
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = False
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SET asysymbol = True
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = False
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SET designentry = vhdl
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SET device = xc6slx45
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SET devicefamily = spartan6
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SET flowvendor = Foundation_ISE
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SET formalverification = False
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SET foundationsym = False
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SET implementationfiletype = Ngc
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SET package = csg324
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SET removerpms = False
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SET simulationfiles = Structural
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SET speedgrade = -3
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SET verilogsim = False
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SET vhdlsim = False
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# END Project Options
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# BEGIN Select
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SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
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# END Select
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# BEGIN Parameters
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CSET component_name=icon
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CSET enable_jtag_bufg=true
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CSET number_control_ports=2
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CSET use_ext_bscan=false
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CSET use_softbscan=false
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CSET use_unused_bscan=false
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CSET user_scan_chain=USER1
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# END Parameters
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GENERATE
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# CRC: 7da1f376
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