147 lines
6.3 KiB
Plaintext
147 lines
6.3 KiB
Plaintext
::****************************************************************************
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:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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::
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:: This file contains confidential and proprietary information
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:: of Xilinx, Inc. and is protected under U.S. and
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:: international copyright and other intellectual property
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:: laws.
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::
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:: DISCLAIMER
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:: This disclaimer is not a license and does not grant any
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:: rights to the materials distributed herewith. Except as
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:: otherwise provided in a valid license issued to you by
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:: Xilinx, and to the maximum extent permitted by applicable
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:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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:: (2) Xilinx shall not be liable (whether in contract or tort,
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:: including negligence, or under any other theory of
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:: liability) for any loss or damage of any kind or nature
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:: related to, arising under or in connection with these
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:: materials, including for any direct, or any indirect,
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:: special, incidental, or consequential loss or damage
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:: (including loss of data, profits, goodwill, or any type of
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:: loss or damage suffered as a result of any action brought
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:: by a third party) even if such damage or loss was
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:: reasonably foreseeable or Xilinx had been advised of the
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:: possibility of the same.
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::
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:: CRITICAL APPLICATIONS
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:: Xilinx products are not designed or intended to be fail-
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:: safe, or for use in any application requiring fail-safe
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:: performance, such as life-support or safety devices or
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:: systems, Class III medical devices, nuclear facilities,
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:: applications related to the deployment of airbags, or any
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:: other applications that could lead to death, personal
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:: injury, or severe property or environmental damage
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:: (individually and collectively, "Critical
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:: Applications"). Customer assumes the sole risk and
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:: liability of any use of Xilinx products in Critical
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:: Applications, subject only to applicable laws and
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:: regulations governing limitations on product liability.
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::
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:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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:: PART OF THIS FILE AT ALL TIMES.
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::
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::****************************************************************************
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:: ____ ____
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:: / /\/ /
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:: /___/ \ / Vendor : Xilinx
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:: \ \ \/ Version : 3.92
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:: \ \ Application : MIG
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:: / / Filename : readme.txt
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:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
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:: \ \ / \ Date Created : Fri Feb 06 2009
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:: \___\/\___\
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::
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:: Device : Spartan-6
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:: Design Name : DDR/DDR2/DDR3/LPDDR
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:: Purpose : Information about par folder
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:: Reference :
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:: Revision History :
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::****************************************************************************
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This folder has the batch files to synthesize using XST or Synplify Pro and
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implement the design either in "Command Line Mode" or in "GUI Mode".
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Steps to run the design using the ise_flow (batch mode):
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1. Executing the "ise_flow.bat" file synthesizes the design using XST or
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Synplify Pro and does implement the design.
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a. First it removes the XST/Synplify Pro report files, implementation
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files, supporting scripts, the generated chipscope designs (if
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enabled) and the ISE project files (if exist any on previous runs)
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b. Synthesizes the design either with XST or Synplicity
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c. Implements the design with ISE.
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2. After the design is run, it creates ise_flow_results.txt file that will have
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the ISE log information.
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Steps to run the design using the create_ise (GUI mode - for XST cases only):
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1. This file will appear for XST cases only.
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2. On executing the "create_ise.bat" file creates "test.xise" project file
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and set all the properties of the design selected.
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3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
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4. In Linux operating systems, test.xise project can be invoked by executing the command
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'ise test.xise' from the terminal.
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Other files in PAR folder :
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* "ddr2.ucf" file is the constraint file for the design.
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It has clock constraints, location constraints and IO standards.
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* "mem_interface_top.ut" file has the options for the Configuration file
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generation i.e. the "ddr2.bit" file to run in batch mode.
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* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
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implementation files, supporting scripts, the generated chipscope designs
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(if enabled) and the ISE project files.
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* "set_ise_prop.tcl" file has all the properties that are to be
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set in GUI mode.
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* "ise_run.txt" file has synthesis options for the XST tool.
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This file is used for batch mode.
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* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
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generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
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EDIF/NGC files, you must execute the following commands before starting
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synthesis and PAR.
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coregen -b ila_coregen.xco
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coregen -b icon_coregen.xco
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coregen -b vio_coregen.xco
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Note : When you generate the design using "Debug Signals for Memory Controller"
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option Enable, the above mentioned ChipScope coregen commands are printed
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into ise_flow.bat and create_ise.bat files. The ddr2 rtl file
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will have the design debug signals portmapped to vio and icon
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ChipScope modules.
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* At the start of a Chip Scope Analyzer project, all of the signals in
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every core have generic names. "ddr2.cdc" is a file that contains
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all the signal names of all cores. Upon importing this file, signal names are
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renamed to the specified names in "ddr2.cdc" file. This file will work
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for the generated designs from MIG. If any of the design parameter values
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are changed after generating the design, this file will not work.
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For Multiple Controller designs, signal names provided in CDC file are of
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the controller that is enabled for Debug in the GUI.
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synth folder:
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1. mem_interface_top_synp.sdc
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2. script_synp.tcl
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3. ddr2.prj
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4. ddr2.lso
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mem_interface_top_synp.sdc and script_synp.tcl files are being used by
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Synplify Pro and ddr2.prj and ddr2.lso are being used by XST.
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