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add stream output start of packet (SOP)

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This commit is contained in:
Benjamin Krill
2013-12-04 15:43:22 +01:00
parent 19caae41ef
commit 6f69d97683
6 changed files with 367 additions and 369 deletions
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8
fpga/f2p/f2p_strm_top.vhd
View File

@@ -47,6 +47,7 @@ entity f2p_strm_top is
-- streaming bus
strm_in_data_o : out std_logic_vector(31 downto 0);
strm_in_eop_o : out std_logic;
strm_in_sop_o : out std_logic;
strm_in_en_o : out std_logic;
strm_in_busy_i : in std_logic;
strm_out_slv_reqs_i : in std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
@@ -61,6 +62,7 @@ architecture f2p_strm_top of f2p_strm_top is
signal rp_read_cnt : unsigned(23 downto 0);
signal strm_data : std_logic_vector(31 downto 0);
signal strm_eop : std_logic;
signal strm_sop : std_logic;
signal strm_en : std_logic;
signal wp_wr : std_logic;
@@ -78,6 +80,7 @@ architecture f2p_strm_top of f2p_strm_top is
begin
strm_in_data_o <= strm_data;
strm_in_eop_o <= strm_eop;
strm_in_sop_o <= strm_sop;
strm_in_en_o <= strm_en;
f2p_master_0: entity work.f2p_master
@@ -121,6 +124,7 @@ begin
strm_data <= (others => '0');
strm_en <= '0';
strm_eop <= '0';
strm_sop <= '0';
elsif rising_edge(clk) then
-- get next packet and stream to slaves
if rp_rd = '1' then
@@ -134,9 +138,13 @@ begin
-- stream data
strm_en <= '0';
strm_eop <= '0';
strm_sop <= '0';
if rp_rd = '1' then
strm_en <= '1';
strm_data <= rp_dat;
if rp_read_cnt = x"000000" then
strm_sop <= '1';
end if;
if rp_read_cnt = x"000001" then
strm_eop <= '1';
end if;

3
fpga/f2p/f2p_strm_top_tb.vhd
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@@ -34,6 +34,7 @@ ARCHITECTURE rtl OF f2p_strm_top_tb IS
signal strm_in_type : std_logic_vector( 3 downto 0);
signal strm_in_data : std_logic_vector(31 downto 0);
signal strm_in_eop : std_logic;
signal strm_in_sop : std_logic;
signal strm_in_en : std_logic;
signal strm_in_busy : std_logic;
constant STRM_OUT_SLV_CNT : integer := 1;
@@ -116,6 +117,7 @@ BEGIN
-- streaming bus
strm_in_data_o => strm_in_data,
strm_in_eop_o => strm_in_eop,
strm_in_sop_o => strm_in_sop,
strm_in_en_o => strm_in_en,
strm_in_busy_i => strm_in_busy,
strm_out_slv_reqs_i => strm_out_slv_reqs,
@@ -138,6 +140,7 @@ BEGIN
-- streaming bus
strm_in_data_i => strm_in_data,
strm_in_eop_i => strm_in_eop,
strm_in_sop_i => strm_in_sop,
strm_in_en_i => strm_in_en,
strm_in_busy_o => strm_in_busy,
strm_out_req_o => ddr2_strm_out_req,

23
fpga/f2p/strm_package.vhd
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@@ -26,11 +26,14 @@ use ieee.numeric_std.all;
-- GENERAL PKT FORMAT
-- --------------------------------------------------------
-- Type (4bit)
-- _Tag (4bit)
-- Plength (7bit) data length (0 = 0byte, 0x7f = 127 * 4byte)
-- 31 16|15 0
-- header |Type ________|___PLenght______|
-- header |Type_Tag________|___PLenght______|
-- data |... type defined data/fields ... |
--
-- --------------------------------------------------------
-- --------------------------------------------------------
-- DDR2 WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
@@ -40,18 +43,34 @@ use ieee.numeric_std.all;
-- --------------------------------------------------------
-- header0 |0 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- header1 | |_______SIZE_____| -- SIZE in 4byte to read
-- --------------------------------------------------------
-- --------------------------------------------------------
-- --------------------------------------------------------
-- --------------------------------------------------------
-- REGFILE WRITE TYPE FORMAT
-- --------------------------------------------------------
-- header |1 ________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- data | 32 bit data |
--
-- REGFILE READ TYPE FORMAT
-- --------------------------------------------------------
-- header |0TAG________ADDR|ESS_____________| -- ADDRESS 4byte aligned
-- --------------------------------------------------------
-- --------------------------------------------------------
package strm_package is
constant STRM_TYPE_HIGH : integer := 31;
constant STRM_TYPE_LOW : integer := 28;
constant STRM_TAG_HIGH : integer := 27;
constant STRM_TAG_LOW : integer := 24;
constant STRM_LENGTH_HIGH : integer := 23;
constant STRM_LENGTH_LOW : integer := 0;
-- SLAVE TYPE IDs
constant STRM_TYPE_DDR2 : std_logic_vector(3 downto 0) := "0001";
constant STRM_TYPE_REGFILE : std_logic_vector(3 downto 0) := "0010";
-- DDR2
constant STRM_DDR2_BUS : integer := 0;
constant STRM_DDR2_ADR_HIGH : integer := 27;
constant STRM_DDR2_ADR_LOW : integer := 0;
constant STRM_DDR2_ACCESS : integer := 31;