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Benjamin Krill
2013-10-02 10:43:54 +02:00
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304
firmware/include/autovector.h Normal file
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// Copyright (C) 2010 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/** \file usbjt.h
*
* To use usbjt, you must tell the linker where to put the IN2JT.
* It must lie on a page boundary or your interrupts won't work right.
*
* example:
* -Wl"-b INT2JT = 0x1A00"
*
* Make sure that INT2JT doesn't overlap your other code!
*
* Unlike the standard fx2 interrupts (\ref fx2ints.h), the autovectored
* interrupts are defined in assemply and have pre-written function names.
* Be sure to override the functions defined in this header or your
* interrupt handler will not be called.
**/
#ifndef USBJT_H
#define USBJT_H
#include "fx2regs.h"
// this causes usbjt to be included from the lib
// not used for anything
extern volatile BYTE INT2JT;
extern volatile BYTE INT4JT;
/**
* Enable all interrupts (EA=1) separate from this macro.
* This macro causes the autovector assembly for int2 interrupts
* to be overlayed at 0x43. In addition, the jump table for the
* interrupts will be included in the firmware. The jump table
* must lie on a page boundary. This is done by passing the linker
* arguments to sdcc.
*
* \code
* sdcc <files> -Wl"-b INT2JT = 0xaddr"
* \endcode
**/
#define USE_USB_INTS() {BYTE dummy=INT2JT;\
EUSB=1;\
INTSETUP|=bmAV2EN;}
/** This macro causes the autovector assemby for int4 to be overlayed
* at 0x53. Don't use this if you want external pin generated int4 interrupts
* and want to define your own interrupt handler. It is possible to use
* usb interrupts with autovectoring and not use GPIF interrupts but GPIF
* interrupts require the USB jump table. (You can't USE your own usb interrupt
* handler if you want to enable GPIF interrupts.)
**/
#define USE_GPIF_INTS() {BYTE dummy=INT4JT;\
EIEX4=1;\
INTSETUP|=bmAV4EN|INT4IN;}
#define CLEAR_USBINT() EXIF &= ~0x10
#define CLEAR_GPIF() EXIF &= ~0x40
#define ENABLE_SUDAV() USBIE|=bmSUDAV
#define CLEAR_SUDAV() CLEAR_USBINT(); USBIRQ=bmSUDAV
#define ENABLE_SUTOK() USBIE|=bmSUTOK;
#define CLEAR_SUTOK() CLEAR_USBINT(); USBIRQ=bmSUTOK
#define ENABLE_SOF() USBIE|=bmSOF
#define CLEAR_SOF() CLEAR_USBINT(); USBIRQ=bmSOF
#define ENABLE_SUSPEND() USBIE|=bmSUSP
#define CLEAR_SUSPEND() CLEAR_USBINT(); USBIRQ=bmSUSP
#define ENABLE_USBRESET() USBIE|= bmURES
#define CLEAR_USBRESET() CLEAR_USBINT(); USBIRQ=bmURES
#define ENABLE_HISPEED() USBIE|=bmHSGRANT
#define CLEAR_HISPEED() CLEAR_USBINT(); USBIRQ=bmHSGRANT
#define ENABLE_EP0IN() EPIE|=bmEP0IN
#define CLEAR_EP0IN() CLEAR_USBINT(); EPIRQ=bmEP0IN
#define ENABLE_EP1IN() EPIE|=bmEP1IN
#define CLEAR_EP1IN() CLEAR_USBINT(); EPIRQ=bmEP1IN
#define ENABLE_EP2() EPIE|=bmEP2
#define CLEAR_EP2() CLEAR_USBINT(); EPIRQ=bmEP2
#define ENABLE_EP6() EPIE|=bmEP6
#define CLEAR_EP6() CLEAR_USBINT(); EPIRQ=bmEP6
#define ENABLE_EP2ISOERR() USBERRIE |= bmISOEP2
#define CLEAR_EP2ISOERR() CLEAR_USBINT(); USBERRIRQ = bmISOEP2
#define ENABLE_EP6PF() EP6FIFOIE |= bmBIT2
#define CLEAR_EP6PF() CLEAR_GPIF(); EP6FIFOIRQ=bmBIT2
#define ENABLE_EP6FF() EP6FIFOIE |= bmBIT0
#define CLEAR_EP6FF() CLEAR_GPIF(); EP6FIFOIRQ=bmBIT0
#define ENABLE_GPIFDONE() GPIFIE |= 0x01;
#define CLEAR_GPIFDONE() CLEAR_GPIF(); GPIFIRQ = 0x01;
#define ENABLE_GPIFWF() GPIFIE |= 0x02;
#define CLEAR_GPIFWF() GLEAR_GPIF(); GPIFIRQ = 0x02;
/**
* ez-usb has 12 built in ISRs, to get
* sdcc to put these USB ISRs immediately
* after the other ISRs (and not waste space)
* we start at 13
**/
typedef enum {
SUDAV_ISR = 13,
SOF_ISR,
SUTOK_ISR,
SUSPEND_ISR,
USBRESET_ISR,
HISPEED_ISR,
EP0ACK_ISR,
EP0IN_ISR,
EP0OUT_ISR,
EP1IN_ISR,
EP1OUT_ISR,
EP2_ISR,
EP4_ISR,
EP6_ISR,
EP8_ISR,
IBN_ISR,
EP0PING_ISR,
EP1PING_ISR,
EP2PING_ISR,
EP4PING_ISR,
EP6PING_ISR,
EP8PING_ISR,
ERRLIMIT_ISR,
EP2ISOERR_ISR,
EP4ISOERR_ISR,
EP6ISOERR_ISR,
EP8ISOERR_ISR,
RESERVED_ISR,
EP2PF_ISR,
EP4PF_ISR,
EP6PF_ISR,
EP8PF_ISR,
EP2EF_ISR,
EP4EF_ISR,
EP6EF_ISR,
EP8EF_ISR,
EP2FF_ISR,
EP4FF_ISR,
EP6FF_ISR,
EP8FF_ISR,
GPIFDONE_ISR,
GPIFWF_ISR
} USB_ISR;
// you must include the predef of these in the file with your main
// so lets just define them here
void
sudav_isr()
__interrupt SUDAV_ISR;
void
sof_isr()
__interrupt SOF_ISR;
void
sutok_isr()
__interrupt SUTOK_ISR;
void
suspend_isr()
__interrupt SUSPEND_ISR;
void
usbreset_isr()
__interrupt USBRESET_ISR;
void
hispeed_isr()
__interrupt HISPEED_ISR;
void
ep0ack_isr()
__interrupt EP0ACK_ISR;
void
ep0in_isr()
__interrupt EP0IN_ISR;
void
ep0out_isr()
__interrupt EP0OUT_ISR;
void
ep1in_isr()
__interrupt EP1IN_ISR;
void
ep1out_isr()
__interrupt EP1OUT_ISR;
void
ep2_isr()
__interrupt EP2_ISR;
void
ep4_isr()
__interrupt EP4_ISR;
void
ep6_isr()
__interrupt EP6_ISR;
void
ep8_isr()
__interrupt EP8_ISR;
void
ibn_isr()
__interrupt IBN_ISR;
void
ep0ping_isr()
__interrupt EP0PING_ISR;
void
ep1ping_isr()
__interrupt EP1PING_ISR;
void
ep2ping_isr()
__interrupt EP2PING_ISR;
void
ep4ping_isr()
__interrupt EP4PING_ISR;
void
ep6ping_isr()
__interrupt EP6PING_ISR;
void
ep8ping_isr()
__interrupt EP8PING_ISR;
void
errlimit_isr()
__interrupt ERRLIMIT_ISR;
void
ep2isoerr_isr()
__interrupt EP2ISOERR_ISR;
void
ep4isoerr_isr()
__interrupt EP4ISOERR_ISR;
void
ep6isoerr_isr()
__interrupt EP6ISOERR_ISR;
void
ep8isoerr_isr()
__interrupt EP8ISOERR_ISR;
void
spare_isr()
__interrupt RESERVED_ISR; // not used
// gpif ints
void
ep2pf_isr()
__interrupt EP2PF_ISR;
void
ep4pf_isr()
__interrupt EP4PF_ISR;
void
ep6pf_isr()
__interrupt EP6PF_ISR;
void
ep8pf_isr()
__interrupt EP8PF_ISR;
void
ep2ef_isr()
__interrupt EP2EF_ISR;
void
ep4ef_isr()
__interrupt EP4EF_ISR;
void
ep6ef_isr()
__interrupt EP6EF_ISR;
void
ep8ef_isr()
__interrupt EP8EF_ISR;
void
ep2ff_isr()
__interrupt EP2FF_ISR;
void
ep4ff_isr()
__interrupt EP4FF_ISR;
void
ep6ff_isr()
__interrupt EP6FF_ISR;
void
ep8ff_isr()
__interrupt EP8FF_ISR;
void
gpifdone_isr()
__interrupt GPIFDONE_ISR;
void
gpifwf_isr()
__interrupt GPIFWF_ISR;
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
* Functions for causing delays.
* */
#ifndef DELAY_H
#define DELAY_H
#include "fx2types.h"
/**
* 0-65536 millis
**/
void delay(WORD millis);
/**
* See TRM 15-14,15-15
* some registers (r/w) require syncdelay after
*
* up to the programmer to determine which sync is needed.
* for standard 48mhz clock w/ 48mhz IFCONFIG 3 nops is sufficient.
*
* slower clock and faster ifclock require more delay
*
* min delay = roof ( 1.5 x (ifclock/clkout + 1) )
*
* Minimum IFCLOCK is 5mhz but you have to use an
* external clock source to go below 30mhz
*
* IFCLKSRC 1 = internal, 0=external
* 3048mhz 0 = 30mhz, 1 = 48mzh
*
* Figure your own sync delay out if IFCLKSRC=0.
**/
#define NOP __asm nop __endasm
/**
* SYNCDELAY2 can work for the following clock speeds
*
* ifclk/clk
* \li 48/12
*
* ceil(1.5 * (20.8 / 83.3 + 1)) = 2
*
* \see NOP
*
**/
#define SYNCDELAY2 NOP; NOP
/**
* SYNCDELAY3 can work for the following clock speeds
*
* ifcfg/clk
* \li 48/24
* \li 48/48
* \li 30/12
* \li 30/24
*
* \see NOP
**/
#define SYNCDELAY3 NOP; NOP; NOP
/**
* SYNCDELAY4 should be used for the following speeds
*
* ifcfg/clk
* \li 30/48
*
* \see NOP
**/
#define SYNCDELAY4 NOP; NOP; NOP; NOP
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
* Functions and macros for working with endpoints.
* */
#ifndef EPUTILS_H
#define EPUTILS_H
#include "fx2types.h"
/**
* NOTE you can't use these unless you define SYNCDELAY
* as a macro or function. The reason is that SYNCDELAY
* needs to be longer or shorter depending on your IFCONFIG
* settings.
* See delay.h
*
* Example:
* \code
* #define SYNCDELAY SYNCDELAY4 // SYNCDELAY4 from delay.h
* \endcode
*
*
**/
/**
* Stalls EP0.
**/
#define STALLEP0() EP0CS |= bmEPSTALL
/**
* \brief Reset the toggle on an endpoint.
* To use this, the endpoint needs bit 8 to be IN=1,OUT=0
**/
#define RESETTOGGLE(ep) TOGCTL = (ep&0x0F) + ((ep&0x80)>>3); TOGCTL |= bmRESETTOGGLE
/**
* RESETFIFO should not use 0x80|epnum for IN endpoints
* Only use 0x02, 0x04, 0x06, 0x06 for ep value
**/
#define RESETFIFO(ep) {FIFORESET=0x80; SYNCDELAY;\
FIFORESET=ep; SYNCDELAY;\
FIFORESET=0x00; SYNCDELAY;}
/**
* Quickly reset all endpoint FIFOS.
**/
#define RESETFIFOS() {FIFORESET=0x80; SYNCDELAY;\
FIFORESET=0x02; SYNCDELAY;\
FIFORESET=0x04; SYNCDELAY;\
FIFORESET=0x06; SYNCDELAY;\
FIFORESET=0x08; SYNCDELAY;\
FIFORESET=0x00; SYNCDELAY;}
/**
* Continually read available bytes from endpoint0 into dst, wait
* until more bytes are available, and loop until len bytes have
* been read.
**/
void readep0(BYTE * dst, WORD len);
/**
* Write bytes from src to ep0, allowing host to transfer data
* between 64 byte blocks.
**/
void writeep0(BYTE * src, WORD len);
#endif

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// Copyright (C) 2010 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
* Define the standard fx2 interrupts. For int2 and int4 autovector
* interrupts see \ref autovector.h
*
* To enable an interrupt, simply define an interrupt handler function
* and use the appropriate ENABLE_* macro. Interrupt enable macros
* do not enable interrupts globally. Use EA=1 to enable interrupts.
*
* \code
* void main() {
* ENABLE_RESUME();
* EA=1;
* ...
* }
*
* void handle_resume() interrupt RESUME_ISR {
* CLEAR_RESUME();
* }
* \endcode
*
* */
/**
* \brief interrupt numbers for standard fx2 interrupts
**/
typedef enum {
IE0_ISR = 0, ///< External interrupt 0
TF0_ISR, ///< Timer 0 interrupt
IE1_ISR, ///< External interrupt 1
TF1_ISR, ///< Timer 1 interrupt
TI_0_ISR, ///< Serial port 0 transmit or receive interrupt
TF2_ISR, ///< Timer 2 interrupt
RESUME_ISR, ///< Resume interrupt
TI_1_ISR, ///< Serial port 1 transmit or receive interrupt
USBINT_ISR, ///< Usb Interrupt. An interrupt handler for this should only be used if not using auto vectored interrupts with int2
I2CINT_ISR, ///< I2C Bus interrupt
IE4_ISR, ///< External interrupt 4. An interrupt handler for this should only be used if not using auto vectored interrupts with int4
IE5_ISR, ///< External interrupt 5
IE6_ISR, ///< External interrupt 6
} FX2_ISR;
/**
* \brief Enable the timer 0 interrupt.
*
* There is not CLEAR_TIMER0 because the timer interrupt flag
* is automatically cleared when the isr is called.
**/
#define ENABLE_TIMER0() ET0=1
/**
* \brief Enable timer 1 interrupt
* There is no CLEAR_TIMER1 because the timer interrupt flag
* is automatically cleared when the isr is called.
**/
#define ENABLE_TIMER1() ET1=1
/**
* \brief Enable timer 2 interrupt
*
* This is the same interrupt whether timer 2 overflowed or
* for the external EXF2 flag.
**/
#define ENABLE_TIMER2() ET2=1
/**
* \brief Clear timer 2 interrupt
*
* Clears both the TF2 AND EXF2 flag
**/
#define CLEAR_TIMER2() TF2=0;EXF2=0;
/**
* \brief Enable the Resume Interrupt. Requires EA=1 separately.
**/
#define ENABLE_RESUME() ERESI = 1
/**
* \brief Clear the resume interrupt. Use within the resume
* interrupt handler.
**/
#define CLEAR_RESUME() RESI=0
#define ENABLE_INT4()
/**
* \brief
* Enable external interupt for int5#
**/
#define ENABLE_INT5() EIEX5=1
/**
* \brief
* Clear int5# interrupt
**/
#define CLEAR_INT5() EXIF &= ~0x80

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
* Macros for simple common tasks in fx2 firmware.
* */
#ifndef FX2MACROS_H
#define FX2MACROS_H
#include "fx2regs.h"
#include "fx2types.h"
#define MSB(addr) (BYTE)(((WORD)(addr) >> 8) & 0xff)
#define LSB(addr) (BYTE)((WORD)(addr) & 0xff)
#define MAKEWORD(msb,lsb) (((WORD)msb << 8) | lsb)
#define MSW(dword) (WORD)((dword >> 16) & 0xffff)
#define LSW(dword) (WORD)(dword & 0xffff)
#define MAKEDWORD(msw,lsw) (((DWORD)msw << 16) | lsw)
// clock stuff
/**
* \brief Used for getting and setting the CPU clock speed.
**/
typedef enum { CLK_12M = 0, CLK_24M, CLK_48M } CLK_SPD;
/**
* \brief Evaluates to a CLK_SPD enum.
**/
#define CPUFREQ (CLK_SPD)((CPUCS & bmCLKSPD) >> 3)
/**
* \brief Sets the cpu to operate at a specific
* clock speed.
**/
#define SETCPUFREQ(SPD) CPUCS = (CPUCS & ~bmCLKSPD) | (SPD << 3)
/**
* \brief Evaluates to a DWORD value representing
* the clock speed in cycles per second.
*
* Speeds:
*
* \li 12000000L
* \li 24000000L
* \li 48000000L
*
**/
#define XTAL (CPUFREQ==CLK_12M ? 12000000L :\
CPUFREQ==CLK_24M ? 24000000L : 48000000L)
/**
* \brief Evaluates to the i2c bus frequency in cyles per
* second.
*
* Speeds:
*
* \li 400000L
* \li 100000L
*
**/
#define I2CFREQ ((I2CTL & bm400KHZ) ? 400000L : 100000L)
#define IFFREQ (IFCONFIG & bm3048MHZ ? 48000000L : 30000000L)
#define SETIF30MHZ() IFCONFIG &= ~bm3048MHZ
#define SETIF48MHZ() IFCONFIG |= bm3048MHZ
// eeprom stuff
#define EEPROM_TWO_BYTE (I2CS & bmBIT4)
/**
* \brief Cause the device to disconnect and reconnect to USB. This macro
* unconditionally renumerates the device no matter how the firmware is loaded.
*
* <b>NOTE</b> Windows really doesn't like this if the firmware is loaded
* from an eeprom. You'll see information messages about the device not
* working properly. On the other hand, if you are changing the device
* descriptor, e.g., the vendor and product id, when downloading firmware to the device,
* you'll need to use this macro instead of the
* standard RENUMERATE macro.
**/
#define RENUMERATE_UNCOND() USBCS|=bmDISCON|bmRENUM;delay(1500);USBCS&=~bmDISCON
/**
* \brief Cause the device to disconnect and reconnect to the USB bus. This macro
* doesn't do anything if the firmware is loaded from an eeprom.
**/
#define RENUMERATE() if(!(USBCS&bmRENUM)) {USBCS|=bmDISCON|bmRENUM;delay(1500);USBCS &= ~bmDISCON;}
// interrupts
// USB interrupts are in usbjt.h
/**
* \brief TRUE if the FX2 has transitioned to high speed on the USB bus..
**/
#define HISPEED (USBCS&bmHSM)
/**
* \brief Evaluates to TRUE if a remote wakeup event has occurred.
**/
#define REMOTE_WAKEUP() (((WAKEUPCS & bmWU) && (WAKEUPCS & bmWUEN)) || ((WAKEUPCS & bmWU2) && (WAKEUPCS & bmWU2EN)))
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
*
* This is the basic header/register file for working with the cypress fx2
* (cyc768013) and variants 8051 chipset. It contains the special function
* register definitions as well as the special configuration registers
* addresses.
*
* The TRM for the fx2 chip contains the full documentation for what each of
* these registers do.
*
* */
/** \mainpage FX2LIB Documentation
* \verbinclude README
**/
/** \example fw.c
* The firmware framework allows for easily beginning a new firware project.
**/
#ifndef FX2REGS_H
#define FX2REGS_H
#include "fx2types.h"
__xdata __at 0xE400 volatile BYTE GPIF_WAVE_DATA;
__xdata __at 0xE480 volatile BYTE RES_WAVEDATA_END;
// General Configuration
__xdata __at 0xE600 volatile BYTE CPUCS; ///< Control & Status
__xdata __at 0xE601 volatile BYTE IFCONFIG; ///< Interface Configuration
__xdata __at 0xE602 volatile BYTE PINFLAGSAB; ///< FIFO FLAGA and FLAGB Assignments
__xdata __at 0xE603 volatile BYTE PINFLAGSCD; ///< FIFO FLAGC and FLAGD Assignments
__xdata __at 0xE604 volatile BYTE FIFORESET; ///< Restore FIFOS to default state
__xdata __at 0xE605 volatile BYTE BREAKPT; ///< Breakpoint
__xdata __at 0xE606 volatile BYTE BPADDRH; ///< Breakpoint Address H
__xdata __at 0xE607 volatile BYTE BPADDRL; ///< Breakpoint Address L
__xdata __at 0xE608 volatile BYTE UART230; ///< 230 Kbaud clock for T0,T1,T2
__xdata __at 0xE609 volatile BYTE FIFOPINPOLAR; ///< FIFO polarities
__xdata __at 0xE60A volatile BYTE REVID; ///< Chip Revision
__xdata __at 0xE60B volatile BYTE REVCTL; ///< Chip Revision Control
// Endpoint Configuration
__xdata __at 0xE610 volatile BYTE EP1OUTCFG; ///< Endpoint 1-OUT Configuration
__xdata __at 0xE611 volatile BYTE EP1INCFG; ///< Endpoint 1-IN Configuration
__xdata __at 0xE612 volatile BYTE EP2CFG; ///< Endpoint 2 Configuration
__xdata __at 0xE613 volatile BYTE EP4CFG; ///< Endpoint 4 Configuration
__xdata __at 0xE614 volatile BYTE EP6CFG; ///< Endpoint 6 Configuration
__xdata __at 0xE615 volatile BYTE EP8CFG; ///< Endpoint 8 Configuration
__xdata __at 0xE618 volatile BYTE EP2FIFOCFG; ///< Endpoint 2 FIFO configuration
__xdata __at 0xE619 volatile BYTE EP4FIFOCFG; ///< Endpoint 4 FIFO configuration
__xdata __at 0xE61A volatile BYTE EP6FIFOCFG; ///< Endpoint 6 FIFO configuration
__xdata __at 0xE61B volatile BYTE EP8FIFOCFG; ///< Endpoint 8 FIFO configuration
__xdata __at 0xE620 volatile BYTE EP2AUTOINLENH; ///< Endpoint 2 Packet Length H (IN only)
__xdata __at 0xE621 volatile BYTE EP2AUTOINLENL; ///< Endpoint 2 Packet Length L (IN only)
__xdata __at 0xE622 volatile BYTE EP4AUTOINLENH; ///< Endpoint 4 Packet Length H (IN only)
__xdata __at 0xE623 volatile BYTE EP4AUTOINLENL; ///< Endpoint 4 Packet Length L (IN only)
__xdata __at 0xE624 volatile BYTE EP6AUTOINLENH; ///< Endpoint 6 Packet Length H (IN only)
__xdata __at 0xE625 volatile BYTE EP6AUTOINLENL; ///< Endpoint 6 Packet Length L (IN only)
__xdata __at 0xE626 volatile BYTE EP8AUTOINLENH; ///< Endpoint 8 Packet Length H (IN only)
__xdata __at 0xE627 volatile BYTE EP8AUTOINLENL; ///< Endpoint 8 Packet Length L (IN only)
__xdata __at 0xE630 volatile BYTE EP2FIFOPFH; ///< EP2 Programmable Flag trigger H
__xdata __at 0xE631 volatile BYTE EP2FIFOPFL; ///< EP2 Programmable Flag trigger L
__xdata __at 0xE632 volatile BYTE EP4FIFOPFH; ///< EP4 Programmable Flag trigger H
__xdata __at 0xE633 volatile BYTE EP4FIFOPFL; ///< EP4 Programmable Flag trigger L
__xdata __at 0xE634 volatile BYTE EP6FIFOPFH; ///< EP6 Programmable Flag trigger H
__xdata __at 0xE635 volatile BYTE EP6FIFOPFL; ///< EP6 Programmable Flag trigger L
__xdata __at 0xE636 volatile BYTE EP8FIFOPFH; ///< EP8 Programmable Flag trigger H
__xdata __at 0xE637 volatile BYTE EP8FIFOPFL; ///< EP8 Programmable Flag trigger L
__xdata __at 0xE640 volatile BYTE EP2ISOINPKTS; ///< EP2 (if ISO) IN Packets per frame (1-3)
__xdata __at 0xE641 volatile BYTE EP4ISOINPKTS; ///< EP4 (if ISO) IN Packets per frame (1-3)
__xdata __at 0xE642 volatile BYTE EP6ISOINPKTS; ///< EP6 (if ISO) IN Packets per frame (1-3)
__xdata __at 0xE643 volatile BYTE EP8ISOINPKTS; ///< EP8 (if ISO) IN Packets per frame (1-3)
__xdata __at 0xE648 volatile BYTE INPKTEND; ///< Force IN Packet End
__xdata __at 0xE649 volatile BYTE OUTPKTEND; ///< Force OUT Packet End
// Interrupts
__xdata __at 0xE650 volatile BYTE EP2FIFOIE; ///< Endpoint 2 Flag Interrupt Enable
__xdata __at 0xE651 volatile BYTE EP2FIFOIRQ; ///< Endpoint 2 Flag Interrupt Request
__xdata __at 0xE652 volatile BYTE EP4FIFOIE; ///< Endpoint 4 Flag Interrupt Enable
__xdata __at 0xE653 volatile BYTE EP4FIFOIRQ; ///< Endpoint 4 Flag Interrupt Request
__xdata __at 0xE654 volatile BYTE EP6FIFOIE; ///< Endpoint 6 Flag Interrupt Enable
__xdata __at 0xE655 volatile BYTE EP6FIFOIRQ; ///< Endpoint 6 Flag Interrupt Request
__xdata __at 0xE656 volatile BYTE EP8FIFOIE; ///< Endpoint 8 Flag Interrupt Enable
__xdata __at 0xE657 volatile BYTE EP8FIFOIRQ; ///< Endpoint 8 Flag Interrupt Request
__xdata __at 0xE658 volatile BYTE IBNIE; ///< IN-BULK-NAK Interrupt Enable
__xdata __at 0xE659 volatile BYTE IBNIRQ; ///< IN-BULK-NAK interrupt Request
__xdata __at 0xE65A volatile BYTE NAKIE; ///< Endpoint Ping NAK interrupt Enable
__xdata __at 0xE65B volatile BYTE NAKIRQ; ///< Endpoint Ping NAK interrupt Request
__xdata __at 0xE65C volatile BYTE USBIE; ///< USB Int Enables
__xdata __at 0xE65D volatile BYTE USBIRQ; ///< USB Interrupt Requests
__xdata __at 0xE65E volatile BYTE EPIE; ///< Endpoint Interrupt Enables
__xdata __at 0xE65F volatile BYTE EPIRQ; ///< Endpoint Interrupt Requests
__xdata __at 0xE660 volatile BYTE GPIFIE; ///< GPIF Interrupt Enable
__xdata __at 0xE661 volatile BYTE GPIFIRQ; ///< GPIF Interrupt Request
__xdata __at 0xE662 volatile BYTE USBERRIE; ///< USB Error Interrupt Enables
__xdata __at 0xE663 volatile BYTE USBERRIRQ; ///< USB Error Interrupt Requests
__xdata __at 0xE664 volatile BYTE ERRCNTLIM; ///< USB Error counter and limit
__xdata __at 0xE665 volatile BYTE CLRERRCNT; ///< Clear Error Counter EC[3..0]
__xdata __at 0xE666 volatile BYTE INT2IVEC; ///< Interupt 2 (USB) Autovector
__xdata __at 0xE667 volatile BYTE INT4IVEC; ///< Interupt 4 (FIFOS & GPIF) Autovector
__xdata __at 0xE668 volatile BYTE INTSETUP; ///< Interrupt 2&4 Setup
// Input/Output
__xdata __at 0xE670 volatile BYTE PORTACFG; ///< I/O PORTA Alternate Configuration
__xdata __at 0xE671 volatile BYTE PORTCCFG; ///< I/O PORTC Alternate Configuration
__xdata __at 0xE672 volatile BYTE PORTECFG; ///< I/O PORTE Alternate Configuration
__xdata __at 0xE678 volatile BYTE I2CS; ///< Control & Status
__xdata __at 0xE679 volatile BYTE I2DAT; ///< Data
__xdata __at 0xE67A volatile BYTE I2CTL; ///< I2C Control
__xdata __at 0xE67B volatile BYTE XAUTODAT1; ///< Autoptr1 MOVX access
__xdata __at 0xE67C volatile BYTE XAUTODAT2; ///< Autoptr2 MOVX access
#define EXTAUTODAT1 XAUTODAT1
#define EXTAUTODAT2 XAUTODAT2
// USB Control
__xdata __at 0xE680 volatile BYTE USBCS; ///< USB Control & Status
__xdata __at 0xE681 volatile BYTE SUSPEND; ///< Put chip into suspend
__xdata __at 0xE682 volatile BYTE WAKEUPCS; ///< Wakeup source and polarity
__xdata __at 0xE683 volatile BYTE TOGCTL; ///< Toggle Control
__xdata __at 0xE684 volatile BYTE USBFRAMEH; ///< USB Frame count H
__xdata __at 0xE685 volatile BYTE USBFRAMEL; ///< USB Frame count L
__xdata __at 0xE686 volatile BYTE MICROFRAME; ///< Microframe count, 0-7
__xdata __at 0xE687 volatile BYTE FNADDR; ///< USB Function address
// Endpoints
__xdata __at 0xE68A volatile BYTE EP0BCH; ///< Endpoint 0 Byte Count H
__xdata __at 0xE68B volatile BYTE EP0BCL; ///< Endpoint 0 Byte Count L
__xdata __at 0xE68D volatile BYTE EP1OUTBC; ///< Endpoint 1 OUT Byte Count
__xdata __at 0xE68F volatile BYTE EP1INBC; ///< Endpoint 1 IN Byte Count
__xdata __at 0xE690 volatile BYTE EP2BCH; ///< Endpoint 2 Byte Count H
__xdata __at 0xE691 volatile BYTE EP2BCL; ///< Endpoint 2 Byte Count L
__xdata __at 0xE694 volatile BYTE EP4BCH; ///< Endpoint 4 Byte Count H
__xdata __at 0xE695 volatile BYTE EP4BCL; ///< Endpoint 4 Byte Count L
__xdata __at 0xE698 volatile BYTE EP6BCH; ///< Endpoint 6 Byte Count H
__xdata __at 0xE699 volatile BYTE EP6BCL; ///< Endpoint 6 Byte Count L
__xdata __at 0xE69C volatile BYTE EP8BCH; ///< Endpoint 8 Byte Count H
__xdata __at 0xE69D volatile BYTE EP8BCL; ///< Endpoint 8 Byte Count L
__xdata __at 0xE6A0 volatile BYTE EP0CS; ///< Endpoint Control and Status
__xdata __at 0xE6A1 volatile BYTE EP1OUTCS; ///< Endpoint 1 OUT Control and Status
__xdata __at 0xE6A2 volatile BYTE EP1INCS; ///< Endpoint 1 IN Control and Status
__xdata __at 0xE6A3 volatile BYTE EP2CS; ///< Endpoint 2 Control and Status
__xdata __at 0xE6A4 volatile BYTE EP4CS; ///< Endpoint 4 Control and Status
__xdata __at 0xE6A5 volatile BYTE EP6CS; ///< Endpoint 6 Control and Status
__xdata __at 0xE6A6 volatile BYTE EP8CS; ///< Endpoint 8 Control and Status
__xdata __at 0xE6A7 volatile BYTE EP2FIFOFLGS; ///< Endpoint 2 Flags
__xdata __at 0xE6A8 volatile BYTE EP4FIFOFLGS; ///< Endpoint 4 Flags
__xdata __at 0xE6A9 volatile BYTE EP6FIFOFLGS; ///< Endpoint 6 Flags
__xdata __at 0xE6AA volatile BYTE EP8FIFOFLGS; ///< Endpoint 8 Flags
__xdata __at 0xE6AB volatile BYTE EP2FIFOBCH; ///< EP2 FIFO total byte count H
__xdata __at 0xE6AC volatile BYTE EP2FIFOBCL; ///< EP2 FIFO total byte count L
__xdata __at 0xE6AD volatile BYTE EP4FIFOBCH; ///< EP4 FIFO total byte count H
__xdata __at 0xE6AE volatile BYTE EP4FIFOBCL; ///< EP4 FIFO total byte count L
__xdata __at 0xE6AF volatile BYTE EP6FIFOBCH; ///< EP6 FIFO total byte count H
__xdata __at 0xE6B0 volatile BYTE EP6FIFOBCL; ///< EP6 FIFO total byte count L
__xdata __at 0xE6B1 volatile BYTE EP8FIFOBCH; ///< EP8 FIFO total byte count H
__xdata __at 0xE6B2 volatile BYTE EP8FIFOBCL; ///< EP8 FIFO total byte count L
__xdata __at 0xE6B3 volatile BYTE SUDPTRH; ///< Setup Data Pointer high address byte
__xdata __at 0xE6B4 volatile BYTE SUDPTRL; ///< Setup Data Pointer low address byte
__xdata __at 0xE6B5 volatile BYTE SUDPTRCTL; ///< Setup Data Pointer Auto Mode
__xdata __at 0xE6B8 volatile BYTE SETUPDAT[8]; ///< 8 bytes of SETUP data
// GPIF
__xdata __at 0xE6C0 volatile BYTE GPIFWFSELECT; ///< Waveform Selector
__xdata __at 0xE6C1 volatile BYTE GPIFIDLECS; ///< GPIF Done, GPIF IDLE drive mode
__xdata __at 0xE6C2 volatile BYTE GPIFIDLECTL; ///< Inactive Bus, CTL states
__xdata __at 0xE6C3 volatile BYTE GPIFCTLCFG; ///< CTL OUT pin drive
__xdata __at 0xE6C4 volatile BYTE GPIFADRH; ///< GPIF Address H
__xdata __at 0xE6C5 volatile BYTE GPIFADRL; ///< GPIF Address L
__xdata __at 0xE6CE volatile BYTE GPIFTCB3; ///< GPIF Transaction Count Byte 3
__xdata __at 0xE6CF volatile BYTE GPIFTCB2; ///< GPIF Transaction Count Byte 2
__xdata __at 0xE6D0 volatile BYTE GPIFTCB1; ///< GPIF Transaction Count Byte 1
__xdata __at 0xE6D1 volatile BYTE GPIFTCB0; ///< GPIF Transaction Count Byte 0
__xdata __at 0xE6D2 volatile BYTE EP2GPIFFLGSEL; ///< EP2 GPIF Flag select
__xdata __at 0xE6D3 volatile BYTE EP2GPIFPFSTOP; ///< Stop GPIF EP2 transaction on prog. flag
__xdata __at 0xE6D4 volatile BYTE EP2GPIFTRIG; ///< EP2 FIFO Trigger
__xdata __at 0xE6DA volatile BYTE EP4GPIFFLGSEL; ///< EP4 GPIF Flag select
__xdata __at 0xE6DB volatile BYTE EP4GPIFPFSTOP; ///< Stop GPIF EP4 transaction on prog. flag
__xdata __at 0xE6DC volatile BYTE EP4GPIFTRIG; ///< EP4 FIFO Trigger
__xdata __at 0xE6E2 volatile BYTE EP6GPIFFLGSEL; ///< EP6 GPIF Flag select
__xdata __at 0xE6E3 volatile BYTE EP6GPIFPFSTOP; ///< Stop GPIF EP6 transaction on prog. flag
__xdata __at 0xE6E4 volatile BYTE EP6GPIFTRIG; ///< EP6 FIFO Trigger
__xdata __at 0xE6EA volatile BYTE EP8GPIFFLGSEL; ///< EP8 GPIF Flag select
__xdata __at 0xE6EB volatile BYTE EP8GPIFPFSTOP; ///< Stop GPIF EP8 transaction on prog. flag
__xdata __at 0xE6EC volatile BYTE EP8GPIFTRIG; ///< EP8 FIFO Trigger
__xdata __at 0xE6F0 volatile BYTE XGPIFSGLDATH; ///< GPIF Data H (16-bit mode only)
__xdata __at 0xE6F1 volatile BYTE XGPIFSGLDATLX; ///< Read/Write GPIF Data L & trigger transac
__xdata __at 0xE6F2 volatile BYTE XGPIFSGLDATLNOX; ///< Read GPIF Data L, no transac trigger
__xdata __at 0xE6F3 volatile BYTE GPIFREADYCFG; ///< Internal RDY,Sync/Async, RDY5CFG
__xdata __at 0xE6F4 volatile BYTE GPIFREADYSTAT; ///< RDY pin states
__xdata __at 0xE6F5 volatile BYTE GPIFABORT; ///< Abort GPIF cycles
// UDMA
__xdata __at 0xE6C6 volatile BYTE FLOWSTATE; ///<Defines GPIF flow state
__xdata __at 0xE6C7 volatile BYTE FLOWLOGIC; ///<Defines flow/hold decision criteria
__xdata __at 0xE6C8 volatile BYTE FLOWEQ0CTL; ///<CTL states during active flow state
__xdata __at 0xE6C9 volatile BYTE FLOWEQ1CTL; ///<CTL states during hold flow state
__xdata __at 0xE6CA volatile BYTE FLOWHOLDOFF;
__xdata __at 0xE6CB volatile BYTE FLOWSTB; ///<CTL/RDY Signal to use as master data strobe
__xdata __at 0xE6CC volatile BYTE FLOWSTBEDGE; ///<Defines active master strobe edge
__xdata __at 0xE6CD volatile BYTE FLOWSTBHPERIOD; ///<Half Period of output master strobe
__xdata __at 0xE60C volatile BYTE GPIFHOLDAMOUNT; ///<Data delay shift
__xdata __at 0xE67D volatile BYTE UDMACRCH; ///<CRC Upper byte
__xdata __at 0xE67E volatile BYTE UDMACRCL; ///<CRC Lower byte
__xdata __at 0xE67F volatile BYTE UDMACRCQUAL; ///<UDMA In only, host terminated use only
// Endpoint Buffers
__xdata __at 0xE740 volatile BYTE EP0BUF[64]; ///< EP0 IN-OUT buffer
__xdata __at 0xE780 volatile BYTE EP1OUTBUF[64]; ///< EP1-OUT buffer
__xdata __at 0xE7C0 volatile BYTE EP1INBUF[64]; ///< EP1-IN buffer
__xdata __at 0xF000 volatile BYTE EP2FIFOBUF[1024]; ///< 512/1024-byte EP2 buffer (IN or OUT)
__xdata __at 0xF400 volatile BYTE EP4FIFOBUF[1024]; ///< 512 byte EP4 buffer (IN or OUT)
__xdata __at 0xF800 volatile BYTE EP6FIFOBUF[1024]; ///< 512/1024-byte EP6 buffer (IN or OUT)
__xdata __at 0xFC00 volatile BYTE EP8FIFOBUF[1024]; ///< 512 byte EP8 buffer (IN or OUT)
// Error Correction Code (ECC) Registers (FX2LP/FX1 only)
__xdata __at 0xE628 volatile BYTE ECCCFG; ///< ECC Configuration
__xdata __at 0xE629 volatile BYTE ECCRESET; ///< ECC Reset
__xdata __at 0xE62A volatile BYTE ECC1B0; ///< ECC1 Byte 0
__xdata __at 0xE62B volatile BYTE ECC1B1; ///< ECC1 Byte 1
__xdata __at 0xE62C volatile BYTE ECC1B2; ///< ECC1 Byte 2
__xdata __at 0xE62D volatile BYTE ECC2B0; ///< ECC2 Byte 0
__xdata __at 0xE62E volatile BYTE ECC2B1; ///< ECC2 Byte 1
__xdata __at 0xE62F volatile BYTE ECC2B2; ///< ECC2 Byte 2
// Feature Registers (FX2LP/FX1 only)
__xdata __at 0xE50D volatile BYTE GPCR2; ///< Chip Features
/**
* SFRs below
* According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible
* row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B
* row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP
*
* All others have to move a byte to the SRF address
**/
__sfr __at 0x80 IOA;
/* IOA */
__sbit __at 0x80 + 0 PA0;
__sbit __at 0x80 + 1 PA1;
__sbit __at 0x80 + 2 PA2;
__sbit __at 0x80 + 3 PA3;
__sbit __at 0x80 + 4 PA4;
__sbit __at 0x80 + 5 PA5;
__sbit __at 0x80 + 6 PA6;
__sbit __at 0x80 + 7 PA7;
__sfr __at 0x81 SP;
__sfr __at 0x82 DPL;
__sfr __at 0x83 DPH;
__sfr __at 0x84 DPL1;
__sfr __at 0x85 DPH1;
__sfr __at 0x86 DPS;
__sfr __at 0x87 PCON;
__sfr __at 0x88 TCON;
/* TCON */
__sbit __at 0x88 + 0 IT0;
__sbit __at 0x88 + 1 IE0;
__sbit __at 0x88 + 2 IT1;
__sbit __at 0x88 + 3 IE1;
__sbit __at 0x88 + 4 TR0;
__sbit __at 0x88 + 5 TF0;
__sbit __at 0x88 + 6 TR1;
__sbit __at 0x88 + 7 TF1;
__sfr __at 0x89 TMOD;
__sfr __at 0x8A TL0;
__sfr __at 0x8B TL1;
__sfr __at 0x8C TH0;
__sfr __at 0x8D TH1;
__sfr __at 0x8E CKCON;
__sfr __at 0x90 IOB;
/* IOB */
__sbit __at 0x90 + 0 PB0;
__sbit __at 0x90 + 1 PB1;
__sbit __at 0x90 + 2 PB2;
__sbit __at 0x90 + 3 PB3;
__sbit __at 0x90 + 4 PB4;
__sbit __at 0x90 + 5 PB5;
__sbit __at 0x90 + 6 PB6;
__sbit __at 0x90 + 7 PB7;
__sfr __at 0x91 EXIF;
//__sfr __at 0x92 MPAGE;
__sfr __at 0x92 _XPAGE; // same as MPAGE for pdata __sfr access w/ sdcc
__sfr __at 0x98 SCON0;
/* SCON0 */
__sbit __at 0x98 + 0 RI;
__sbit __at 0x98 + 1 TI;
__sbit __at 0x98 + 2 RB8;
__sbit __at 0x98 + 3 TB8;
__sbit __at 0x98 + 4 REN;
__sbit __at 0x98 + 5 SM2;
__sbit __at 0x98 + 6 SM1;
__sbit __at 0x98 + 7 SM0;
__sfr __at 0x99 SBUF0;
__sfr __at 0x9A AUTOPTRH1;
__sfr __at 0x9B AUTOPTRL1;
__sfr __at 0x9D AUTOPTRH2;
__sfr __at 0x9E AUTOPTRL2;
__sfr __at 0xA0 IOC;
/* IOC */
__sbit __at 0xA0 + 0 PC0;
__sbit __at 0xA0 + 1 PC1;
__sbit __at 0xA0 + 2 PC2;
__sbit __at 0xA0 + 3 PC3;
__sbit __at 0xA0 + 4 PC4;
__sbit __at 0xA0 + 5 PC5;
__sbit __at 0xA0 + 6 PC6;
__sbit __at 0xA0 + 7 PC7;
__sfr __at 0xA1 INT2CLR;
__sfr __at 0xA2 INT4CLR;
__sfr __at 0xA8 IE;
/* IE */
__sbit __at 0xA8 + 0 EX0;
__sbit __at 0xA8 + 1 ET0;
__sbit __at 0xA8 + 2 EX1;
__sbit __at 0xA8 + 3 ET1;
__sbit __at 0xA8 + 4 ES0;
__sbit __at 0xA8 + 5 ET2;
__sbit __at 0xA8 + 6 ES1;
__sbit __at 0xA8 + 7 EA;
__sfr __at 0xAA EP2468STAT;
__sfr __at 0xAB EP24FIFOFLGS;
__sfr __at 0xAC EP68FIFOFLGS;
__sfr __at 0xAF AUTOPTRSETUP;
__sfr __at 0xB0 IOD;
/* IOD */
__sbit __at 0xB0 + 0 PD0;
__sbit __at 0xB0 + 1 PD1;
__sbit __at 0xB0 + 2 PD2;
__sbit __at 0xB0 + 3 PD3;
__sbit __at 0xB0 + 4 PD4;
__sbit __at 0xB0 + 5 PD5;
__sbit __at 0xB0 + 6 PD6;
__sbit __at 0xB0 + 7 PD7;
__sfr __at 0xB1 IOE;
__sfr __at 0xB2 OEA;
__sfr __at 0xB3 OEB;
__sfr __at 0xB4 OEC;
__sfr __at 0xB5 OED;
__sfr __at 0xB6 OEE;
__sfr __at 0xB8 IP;
/* IP */
__sbit __at 0xB8 + 0 PX0;
__sbit __at 0xB8 + 1 PT0;
__sbit __at 0xB8 + 2 PX1;
__sbit __at 0xB8 + 3 PT1;
__sbit __at 0xB8 + 4 PS0;
__sbit __at 0xB8 + 5 PT2;
__sbit __at 0xB8 + 6 PS1;
__sfr __at 0xBA EP01STAT;
__sfr __at 0xBB GPIFTRIG;
__sfr __at 0xBD GPIFSGLDATH;
__sfr __at 0xBE GPIFSGLDATLX;
__sfr __at 0xBF GPIFSGLDATLNOX;
__sfr __at 0xC0 SCON1;
/* SCON1 */
__sbit __at 0xC0 + 0 RI1;
__sbit __at 0xC0 + 1 TI1;
__sbit __at 0xC0 + 2 RB81;
__sbit __at 0xC0 + 3 TB81;
__sbit __at 0xC0 + 4 REN1;
__sbit __at 0xC0 + 5 SM21;
__sbit __at 0xC0 + 6 SM11;
__sbit __at 0xC0 + 7 SM01;
__sfr __at 0xC1 SBUF1;
__sfr __at 0xC8 T2CON;
/* T2CON */
__sbit __at 0xC8 + 0 CP_RL2;
__sbit __at 0xC8 + 1 C_T2;
__sbit __at 0xC8 + 2 TR2;
__sbit __at 0xC8 + 3 EXEN2;
__sbit __at 0xC8 + 4 TCLK;
__sbit __at 0xC8 + 5 RCLK;
__sbit __at 0xC8 + 6 EXF2;
__sbit __at 0xC8 + 7 TF2;
__sfr __at 0xCA RCAP2L;
__sfr __at 0xCB RCAP2H;
__sfr __at 0xCC TL2;
__sfr __at 0xCD TH2;
__sfr __at 0xD0 PSW;
/* PSW */
__sbit __at 0xD0 + 0 P;
__sbit __at 0xD0 + 1 FL;
__sbit __at 0xD0 + 2 OV;
__sbit __at 0xD0 + 3 RS0;
__sbit __at 0xD0 + 4 RS1;
__sbit __at 0xD0 + 5 F0;
__sbit __at 0xD0 + 6 AC;
__sbit __at 0xD0 + 7 CY;
__sfr __at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
/* EICON */
__sbit __at 0xD8 + 3 INT6;
__sbit __at 0xD8 + 4 RESI;
__sbit __at 0xD8 + 5 ERESI;
__sbit __at 0xD8 + 7 SMOD1;
__sfr __at 0xE0 ACC;
__sfr __at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
__sbit __at 0xE8 + 0 EUSB;
__sbit __at 0xE8 + 1 EI2C;
__sbit __at 0xE8 + 2 EIEX4;
__sbit __at 0xE8 + 3 EIEX5;
__sbit __at 0xE8 + 4 EIEX6;
__sfr __at 0xF0 B;
__sfr __at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
__sbit __at 0xF8 + 0 PUSB;
__sbit __at 0xF8 + 1 PI2C;
__sbit __at 0xF8 + 2 EIPX4;
__sbit __at 0xF8 + 3 EIPX5;
__sbit __at 0xF8 + 4 EIPX6;
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmSLCS bmBIT6
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* USBERRIE/IRQ */
#define bmERRLIMIT bmBIT0
#define bmISOEP2 bmBIT4
#define bmISOEP4 bmBIT5
#define bmISOEP6 bmBIT6
#define bmISOEP8 bmBIT7
/* Endpoint Interrupt & Enable Registers (EPIE/EPIRQ) */
#define bmEP0IN bmBIT0
#define bmEP0OUT bmBIT1
#define bmEP1IN bmBIT2
#define bmEP1OUT bmBIT3
#define bmEP2 bmBIT4
#define bmEP4 bmBIT5
#define bmEP6 bmBIT6
#define bmEP8 bmBIT7
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define INT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* Endpoint Config (EP[2468]CFG) */
#define bmVALID bmBIT7
#define bmDIR bmBIT6
#define bmTYPE (bmBIT4|bmBIT5)
#define bmTYPE1 bmBIT5
#define bmTYPE0 bmBIT4
#define bmSIZE bmBIT3
/* Endpoint Config (EP[24]CFG) */
#define bmBUF (bmBIT0|bmBIT1)
#define bmBUF1 bmBIT1
#define bmBUF0 bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7
#define bm3048MHZ bmBIT6
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
#define bmWORDWIDE bmBIT0
/* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
features */
#define bmNOAUTOARM bmBIT1
#define bmSKIPCOMMIT bmBIT0
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
/* Chip Feature Register (GPCR2) */
#define bmFULLSPEEDONLY bmBIT4
/* EP 01 status (EP01STAT) */
#define bmEP1INBSY bmBIT2
#define bmEP1OUTBSY bmBIT1
#define bmEP0BSY bmBIT0
#endif /* FX2REGS_H */

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
* define standard types of fixed widths.
* */
#ifndef FXTYPES_H
#define FXTYPES_H
typedef unsigned int WORD;
typedef unsigned char BYTE;
typedef unsigned long DWORD;
typedef unsigned char BOOL;
typedef enum {
FALSE = 0,
TRUE
} BOOL_VALS;
#ifndef NULL
#define NULL (void*)0
#endif
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
#define bmBIT0 1
#define bmBIT1 2
#define bmBIT2 4
#define bmBIT3 8
#define bmBIT4 16
#define bmBIT5 32
#define bmBIT6 64
#define bmBIT7 128
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/*! \file
*
* These functions do the same thing that the Cypress gpif designer expored c file does.
* Instead of including their file directly in your project, you include just the
* generated waveform data. The gpif2dat script in the utils folder will export your
* waveform data to a file that can be included in your project.
* */
#ifndef GPIF_H
#define GPIF_H
#include "fx2types.h"
#define GPIFDONE (GPIFTRIG&0x80)
#define GPIFTC16 (MAKEWORD(GPIFTCB1,GPIFTCB0))
#define GPIFTC32 (MAKEDWORD(MAKEWORD(GPIFTCB3,GPIFTCB2),MAKEWORD(GPIFTCB1,GPIFTCB0)))
/**
* Gpif designer generates a c file with waveform data.
* Copy the WaveData[128] array
* and the InitData[7] to your code somewhere
* Then this function is pretty much the reset of the generated
* code but ported to sdcc.
*
* uses syncdelay of 4 which might not be long enough if peripheral
* runs slower than 30mhz. May not affect anything.
*
* IFCONFIG is set with IFCFG[1:0] = 10 for GPIF master but you still
* have to set the ifclk, polarity, and the rest of the bits
**/
void gpif_init(BYTE * waveform, BYTE * initdata);
/**
* Uses the correct bytes from your flowstates array.
* This may or may not be needed depending on whether
* your waveform data uses flowstates. If you don't
* know if you need them or not, you probably don't.
*
* flowstates should have 36 elements.
* bank should be 0-3
**/
void gpif_setflowstate(BYTE * flowstates, BYTE bank);
//! These defines/functions pretty much out of the TRM 10.4
#define GPIFTRGWR 0
#define GPIFTRGRD 4
typedef enum {
GPIF_EP2 = 0,
GPIF_EP4 = 1,
GPIF_EP6 = 2,
GPIF_EP8 = 3
} GPIF_EP_NUM;
/**
* \brief Simple function to help set the transaction count for gpif
* transactions.
* \param tc 32 bit Transaction Count
**/
void gpif_set_tc32(DWORD tc);
/**
* \brief Simple function to set transaction count for gpif transactions.
* \param tc 16 bit Transaction Count
**/
void gpif_set_tc16(WORD tc);
/**
* Use the gpif to read a single word at a time.
* Read len words and store in res
*
* At least one EPxFIFOCFG has to have wordwide=1 or this
* functions won't transfer both bytes.
**/
void gpif_single_read16(WORD * res, WORD len);
/**
* Use the gpif to write a single word at a time.
* Write len words from data
*
* At leat one EPxFIFOCFG has to have wordwide=1 or this
* function won't transfer both bytes.
**/
void gpif_single_write16(WORD * dat, WORD len);
void gpif_fifo_read(GPIF_EP_NUM ep_num);
void gpif_fifo_write(GPIF_EP_NUM ep_num);
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/** \file i2c.h
* Utilities for reading and writing to i2c devices and as eeproms.
**/
#ifndef I2C_H
#define I2C_H
#include "fx2types.h"
/**
* i2c_write and i2c_read set this to FALSE at the beginning of a
* transaction. If for some reason, the read/write is taking too
* long or not returning, firmware can set this to TRUE to cause the
* routine to abort. (Usually done via an interrupt).
**/
extern volatile __xdata BOOL cancel_i2c_trans;
/**
* \brief write data to i2c bus.
*
* Writes data from addr buffer 1st, then data buffer.
* Either buffer can be NULL (as long as you set lenN to 0).
*
* Two buffers allows writing data all in one i2c write command without
* having to write a hardware address and a data byte with each
* i2c transaction.
*
* \param addr i2c address
* \param len1 length of addr data
* \param addr_buf addr data
* \param len2 length of data
* \param data_buf data bytes
**/
BOOL i2c_write(BYTE addr, WORD len1, BYTE * addr_buf, WORD len2,
BYTE * data_buf);
/**
* \brief read data on the i2c bus.
*
* \param addr i2c address
* \param len number of bytes to read
* \param buf buffer to store data
**/
BOOL i2c_read(BYTE addr, WORD len, BYTE * buf);
/**
* \brief read data from an attached eeprom.
*
* Writes the address of the data to read then reads len bytes into buf.
* This function checks the I2CS register to determine if a one or two
* byte address eepom was detected on the i2c bus. Reading from proms
* at non-standard addresses my require using the i2c_read/write commands
* explicitly.
*
* \param prom_addr eeprom i2c address
* \param addr address of bytes to start reading
* \param len number of bytes to read
* \param buf data buffer
**/
BOOL eeprom_read(BYTE prom_addr, WORD addr, WORD len, BYTE * buf);
/**
* \brief write data to the eeprom
*
* This function checks the I2CS register to determin if a one or two
* two byte eeprom is detected. If the prom is not detected at boot time
* or is connected to alternate addresses, the i2c_read/write commands should
* be used explicitly insread of using this function.
*
* For each byte in buf, the address is written and then the data byte. Many
* proms support writing multiple bytes at the same time. For these, it is
* also better to use i2c_read/write explicitly. This function is rather slow
* but is effective.
*
* \param prom_addr eeprom i2c address
* \param addr address of bytes to start writing
* \param len number of bytes to write
* \param buf data buffer
**/
BOOL eeprom_write(BYTE prom_addr, WORD addr, WORD len, BYTE * buf);
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/** \file lights.h
* macros for turning lights on the EZ-USB development board on and off.
**/
#ifndef LIGHTS_H
#define LIGHTS_H
#include "fx2types.h"
#ifndef FX1
// FX2 Dev board lights
#define D2ONH #0x88 // assembly high byte of light addr
#define D2OFFH #0x80
#define D3ONH #0x98
#define D3OFFH #0x90
#define D4ONH #0xA8
#define D4OFFH #0xA0
#define D5ONH #0xB8
#define D5OFFH #0xB0
volatile __xdata __at 0x8800 BYTE D2ON;
volatile __xdata __at 0x8000 BYTE D2OFF;
volatile __xdata __at 0x9800 BYTE D3ON;
volatile __xdata __at 0x9000 BYTE D3OFF;
volatile __xdata __at 0xA800 BYTE D4ON;
volatile __xdata __at 0xA000 BYTE D4OFF;
volatile __xdata __at 0xB800 BYTE D5ON;
volatile __xdata __at 0xB000 BYTE D5OFF;
#else
// FX1 dev board lights
#define D2ONH #0x80 // assembly high byte of light addr
#define D2OFFH #0x81
#define D3ONH #0x90
#define D3OFFH #0x91
#define D4ONH #0xA0
#define D4OFFH #0xA1
#define D5ONH #0xB0
#define D5OFFH #0xB1
volatile __xdata __at 0x8000 BYTE D2ON;
volatile __xdata __at 0x8100 BYTE D2OFF;
volatile __xdata __at 0x9000 BYTE D3ON;
volatile __xdata __at 0x9100 BYTE D3OFF;
volatile __xdata __at 0xA000 BYTE D4ON;
volatile __xdata __at 0xA100 BYTE D4OFF;
volatile __xdata __at 0xB000 BYTE D5ON;
volatile __xdata __at 0xB100 BYTE D5OFF;
#endif
/**
* Easier to use macros defined below
**/
#define activate_light(LIGHT_ADDR) __asm \
mov __XPAGE, LIGHT_ADDR \
__endasm; __asm \
movx a, @r0 \
__endasm \
/**
* Easy to make lights blink with these macros:
* \code
* WORD ct=0;
* BOOL on=FALSE;
* while (TRUE) {
* if (!ct) {
* on=!on;
* if (on) d2on(); else d2off();
* }
* ++ct;
* }
* \endcode
**/
#define d2on() activate_light(D2ONH)
#define d2off() activate_light(D2OFFH)
#define d3on() activate_light(D3ONH)
#define d3off() activate_light(D3OFFH)
#define d4on() activate_light(D4ONH)
#define d4off() activate_light(D4OFFH)
#define d5on() activate_light(D5ONH)
#define d5off() activate_light(D5OFFH)
#endif

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
/** \file serial.h
* defines functions to print to a serial console with SIO0
**/
#include "fx2types.h"
/**
* This function inits sio0 to use T2CON (timer 2)
* See TRM 14.3.4.1 (Table 14-16)
* Certain baud rates have too high an error rate to work. All baud rates are .16%
* except:
*
* 12MHZ 24MHZ
* \li 57600 -6.99%
* \li 38400 -2.34% -2.34%
* \li 19200 -2.34%
*
* Possible Baud rates:
* \li 2400
* \li 4800
* \li 9600
* \li 19200
* \li 28800
* \li 38400
* \li 57600
*
* Any of these rates should work except 57600 at 12mhz. -2.34% is pushing
* most hardware specs for working. All rates at 48mhz work at .16%
**/
void
sio0_init(WORD baud_rate)
__critical; // baud_rate max should be 57600 since int=2 bytes
/**
putchar('\\n') or putchar('\\r') both transmit \\r\\n
Just use one or the other. (This makes terminal echo easy)
**/
void
putchar(char c);
char
getchar();

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// Copyright (C) 2009 Ubixum, Inc.
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
#ifndef SETUPDAT_H
#define SETUPDAT_H
#include "fx2regs.h"
#include "delay.h"
/** \file setupdat.h
Utilities for handling setup data and vendor commands.
\verbatim
This module needs initialized with a device descriptor.
NOTE that your descriptors need to be located in code memory
to use the SUDPTRH:L to auto transfer the data
and vendor commands handler. You have to provide callbacks.
DEVICE DESCRIPTORS
// copy the dscr_asm file from the lib dir to your
// own project directory, change it how
// you want, and link it against your project
VENDOR COMMANDS
0xA0 is handled by ez-usb firmware. (Upload/Download ram)
0xA1-0xAF is reserved for other ez-usb functions so don't use that
Any other value (Above 0x0C anyway) can be used for device specific
commands.
If you include this file, you need to define a function for vendor
commands even if you don't want to implement any vendor commands.
The function should return TRUE if you handled the command and FALSE
if you didn't. The handle_setup function calls
EP0CS |= bmHSNAK;
before returning so there is no reason to set that bit in your
vendor command handler. (You do need to Set EP0 data and
byte counts appropriately though.)
// return TRUE if you handle the command
// you can directly get SETUPDAT[0-7] for the data sent with the command
BOOL handle_vendorcommand(BYTE cmd) { return FALSE; }
// a note on vencor commands
// this from the usb spec for requesttype
D7 Data Phase Transfer Direction
0 = Host to Device
1 = Device to Host
D6..5 Type
0 = Standard
1 = Class
2 = Vendor
3 = Reserved
D4..0 Recipient
0 = Device
1 = Interface
2 = Endpoint
3 = Other
4..31 = Reserved
// if you want libusb to send data back to the host via ep0, you need to make
// sure the requesttype had 1 in bit 7. This is for libusb on linux anyway.
// set *alt_ifc to the current alt interface for ifc
BOOL handle_get_interface(BYTE ifc, BYTE* alt_ifc) { *ifc=0;*alt_ifc=0;}
// return TRUE if you set the interface requested
// NOTE this function should reconfigure and reset the endpoints
// according to the interface descriptors you provided.
BOOL handle_set_interface(BYTE ifc,BYTE alt_ifc) { return TRUE; }
// handle getting and setting the configuration
// 0 is the default. If you support more than one config
// keep track of the config number and return the correct number
// config numbers are set int the dscr file.
BYTE handle_get_configuration() { return 1; }
// return TRUE if you handle this request
// NOTE changing config requires the device to reset all the endpoints
BOOL handle_set_configuration(BYTE cfg) { return FALSE; }
// ep num (byte 7 is dir 1=IN,0=OUT)
// client needs to reset the endpoint to default state
void handle_reset_ep(BYTE ep) { }
\endverbatim
*/
#define SETUP_VALUE() MAKEWORD(SETUPDAT[3],SETUPDAT[2])
#define SETUP_INDEX() MAKEWORD(SETUPDAT[5],SETUPDAT[4])
#define SETUP_LENGTH() MAKEWORD(SETUPDAT[7],SETUPDAT[6])
#define SETUP_TYPE SETUPDAT[0]
/**
* self_powered is set to FALSE by default. It is
* used for GET_FEATURE requests. Firmware can set it to
* TRUE if the device is not powered by the USB bus.
**/
extern volatile BOOL self_powered;
/**
* remote_wakeup_allowed defaults to FALSE but can be
* set to TRUE with SET_FEATURE from the host. (firmware shouldn't
* set this.)
**/
extern volatile BOOL remote_wakeup_allowed;
//! see TRM 2-3
//! here are the usb setup data commands
//! these are the usb spec pretty much
typedef enum {
GET_STATUS,
CLEAR_FEATURE,
// 0x02 is reserved
SET_FEATURE = 0x03,
// 0x04 is reserved
SET_ADDRESS = 0x05, // this is handled by EZ-USB core unless RENUM=0
GET_DESCRIPTOR,
SET_DESCRIPTOR,
GET_CONFIGURATION,
SET_CONFIGURATION,
GET_INTERFACE,
SET_INTERFACE,
SYNC_FRAME
} SETUP_DATA;
/**
* returns the control/status register for an end point
* (bit 7=1 for IN, 0 for out
**/
__xdata BYTE *ep_addr(BYTE ep);
/*
You can call this function directly if you are polling
for setup data in your main loop.
You can also use the usbjt and enable the sudav isr
and call the function from withing the sudav isr routine
*/
void handle_setupdata();
/**
For devices to properly handle usb hispeed
(This is if your descriptor has high speed and full speed versions
and it should since the fx2lp is a high speed capable device
)
enable both USBRESET and HISPEED interrupts and
call this function to switch the descriptors. This function uses
a __critical section to switch the descriptors and is safe to call
from the hispeed or reset interrupt. See \ref fw.c
\param highspeed Call the function with highspeed = TRUE if
calling because the highspeed interrupt was received.
If calling from usbreset, call with highspeed=false
**/
void handle_hispeed(BOOL highspeed);
/* descriptor types */
#define DSCR_DEVICE_TYPE 1
#define DSCR_CONFIG_TYPE 2
#define DSCR_STRING_TYPE 3
#define DSCR_DEVQUAL_TYPE 6
#define DSCR_OTHERSPD_TYPE 7
/* usb spec 2 */
#define DSCR_BCD 2
/* device descriptor */
#define DSCR_DEVICE_LEN 18
typedef struct {
BYTE dsc_len; // descriptor length (18 for this )
BYTE dsc_type; // dscr type
WORD bcd; // bcd
BYTE dev_class; // device class
BYTE dev_subclass; // sub class
BYTE dev_protocol; // sub sub class
BYTE max_pkt; // max packet size
WORD vendor_id;
WORD product_id;
WORD dev_version; // product version id
BYTE idx_manstr; // manufacturer string index
BYTE idx_devstr; // product string index
BYTE idx_serstr; // serial number index
BYTE num_configs; // number of configurations
} DEVICE_DSCR;
/* config descriptor */
#define DSCR_CONFIG_LEN 9
typedef struct {
BYTE dsc_len; // 9 for this one
BYTE dsc_type; // dscr type
} CONFIG_DSCR;
/* string descriptor */
typedef struct {
BYTE dsc_len;
BYTE dsc_type;
BYTE pstr;
} STRING_DSCR;
#endif