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initial HDET design

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This commit is contained in:
Benjamin Krill
2014-02-17 13:33:46 +01:00
commit d94a97b112
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fpga/src/dvi Submodule

Submodule fpga/src/dvi added at 6a2d616d8a

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fpga/src/i2c/master/i2c_master_bit_ctrl.vhd Normal file
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---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 I2C Master Core; bit-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
--
-- $Date: 2006/10/11 12:10:13 $
-- $Revision: 1.14 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_bit_ctrl.vhd,v $
-- Revision 1.14 2006/10/11 12:10:13 rherveille
-- Added missing semicolons ';' on endif
--
-- Revision 1.13 2006/10/06 10:48:24 rherveille
-- fixed short scl high pulse after clock stretch
--
-- Revision 1.12 2004/05/07 11:53:31 rherveille
-- Fixed previous fix :) Made a variable vs signal mistake.
--
-- Revision 1.11 2004/05/07 11:04:00 rherveille
-- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
--
-- Revision 1.10 2004/02/27 07:49:43 rherveille
-- Fixed a bug in the arbitration-lost signal generation. VHDL version only.
--
-- Revision 1.9 2003/08/12 14:48:37 rherveille
-- Forgot an 'end if' :-/
--
-- Revision 1.8 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.7 2003/02/05 00:06:02 rherveille
-- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
--
-- Revision 1.6 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.5 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.4 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.3 2002/10/30 18:09:53 rherveille
-- Fixed some reported minor start/stop generation timing issuess.
--
-- Revision 1.2 2002/06/15 07:37:04 rherveille
-- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~~~~~\____
-- SDA XX/~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ______/~~~~~~~\___
-- SDA __/~~~~~~~\______
-- x | A | B | C | D | i
--
-- stop SCL _______/~~~~~~~~~~~
-- SDA ==\___________/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ______/~~~~~~~\____
-- SDA XXX===============XX
-- x | A | B | C | D | i
--
--- read SCL ______/~~~~~~~\____
-- SDA XXXXXXX=XXXXXXXXXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_Logic_unsigned.all;
use IEEE.numeric_std.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command completed
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_bit_ctrl;
architecture structural of i2c_master_bit_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
type states is (idle, start_a, start_b, start_c, start_d, start_e,
stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal c_state : states;
signal iscl_oen, isda_oen : std_logic; -- internal I2C lines
signal sda_chk : std_logic; -- check SDA status (multi-master arbitration)
signal dscl_oen : std_logic; -- delayed scl_oen signals
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal clk_en, slave_wait : std_logic; -- clock generation signals
signal ial : std_logic; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process (clk)
begin
if (clk'event and clk = '1') then
dscl_oen <= iscl_oen;
end if;
end process;
slave_wait <= dscl_oen and not sSCL;
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ( (cnt = 0) or (ena = '0') ) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt -1;
clk_en <= '0';
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
signal sta_condition : std_logic; -- start detected
signal sto_condition : std_logic; -- stop detected
signal cmd_stop : std_logic; -- STOP command
signal ibusy : std_logic; -- internal busy signal
begin
-- synchronize SCL and SDA inputs
synch_scl_sda: process(clk, nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
sSCL <= scl_i;
sSDA <= sda_i;
dSCL <= sSCL;
dSDA <= sSDA;
end if;
end if;
end process synch_SCL_SDA;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
detect_sta_sto: process(clk, nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end if;
end process detect_sta_sto;
-- generate i2c-bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
busy <= ibusy;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested (detect during 'idle' state)
gen_al: process(clk, nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
ial <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cmd_stop <= '0';
ial <= '0';
else
if (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
if (c_state = idle) then
ial <= (sda_chk and not sSDA and isda_oen);
else
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
end if;
end if;
end if;
end process gen_al;
al <= ial;
-- generate dout signal, store dout on rising edge of SCL
gen_dout: process(clk)
begin
if (clk'event and clk = '1') then
if (sSCL = '1' and dSCL = '0') then
dout <= sSDA;
end if;
end if;
end process gen_dout;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, c_state, cmd)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or ial = '1') then
c_state <= idle;
cmd_ack <= '0';
iscl_oen <= '1';
isda_oen <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; -- default no acknowledge
if (clk_en = '1') then
case (c_state) is
-- idle
when idle =>
case cmd is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle; -- NOP command
end case;
iscl_oen <= iscl_oen; -- keep SCL in same state
isda_oen <= isda_oen; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA
-- start
when start_a =>
c_state <= start_b;
iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
when start_b =>
c_state <= start_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA
when start_c =>
c_state <= start_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when start_d =>
c_state <= start_e;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when start_e =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
-- stop
when stop_a =>
c_state <= stop_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA
when stop_b =>
c_state <= stop_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_c =>
c_state <= stop_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA
when stop_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA
-- read
when rd_a =>
c_state <= rd_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_b =>
c_state <= rd_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_c =>
c_state <= rd_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
when rd_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA
-- write
when wr_a =>
c_state <= wr_b;
iscl_oen <= '0'; -- keep SCL low
isda_oen <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when wr_b =>
c_state <= wr_c;
iscl_oen <= '1'; -- set SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_c =>
c_state <= wr_d;
iscl_oen <= '1'; -- keep SCL high
isda_oen <= din; -- keep SDA
sda_chk <= '1'; -- check SDA
when wr_d =>
c_state <= idle;
cmd_ack <= '1'; -- command completed
iscl_oen <= '0'; -- set SCL low
isda_oen <= din; -- keep SDA
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture structural;

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fpga/src/i2c/master/i2c_master_byte_ctrl.vhd Normal file
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---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_Logic_unsigned.all;
use IEEE.numeric_std.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = 0) else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;

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---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; top level ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- richard@asics.ws ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- richard@asics.ws ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
--
-- $Date: 2004/03/14 10:17:03 $
-- $Revision: 1.7 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_top.vhd,v $
-- Revision 1.7 2004/03/14 10:17:03 rherveille
-- Fixed simulation issue when writing to CR register
--
-- Revision 1.6 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.5 2003/02/01 02:03:06 rherveille
-- Fixed a few 'arbitration lost' bugs. VHDL version only.
--
-- Revision 1.4 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.3 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.2 2001/11/10 10:52:44 rherveille
-- Changed PRER reset value from 0x0000 to 0xffff, conform specs.
--
--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_Logic_unsigned.all;
use IEEE.numeric_std.all;
entity i2c_master_top is
generic(
ARST_LVL : std_logic := '0' -- asynchronous reset level
);
port (
-- wishbone signals
wb_clk_i : in std_logic; -- master clock input
wb_rst_i : in std_logic := '0'; -- synchronous active high reset
arst_i : in std_logic := not ARST_LVL; -- asynchronous reset
-- wb_adr_i : in unsigned(2 downto 0); -- lower address bits
wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits
wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input
wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output
wb_we_i : in std_logic; -- Write enable input
wb_stb_i : in std_logic; -- Strobe signals / core select signal
wb_cyc_i : in std_logic; -- Valid bus cycle input
wb_ack_o : out std_logic; -- Bus cycle acknowledge output
wb_inta_o : out std_logic; -- interrupt request output signal
-- i2c lines
scl_pad_i : in std_logic; -- i2c clock line input
scl_pad_o : out std_logic; -- i2c clock line output
scl_padoen_o : out std_logic; -- i2c clock line output enable, active low
sda_pad_i : in std_logic; -- i2c data line input
sda_pad_o : out std_logic; -- i2c data line output
sda_padoen_o : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_top;
architecture structural of i2c_master_top is
-- component i2c_master_byte_ctrl is
-- port (
-- clk : in std_logic;
-- rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
-- nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
-- ena : in std_logic; -- core enable signal
--
-- clk_cnt : in unsigned(15 downto 0); -- 4x SCL
--
-- -- input signals
-- start,
-- stop,
-- read,
-- write,
-- ack_in : std_logic;
-- din : in std_logic_vector(7 downto 0);
--
-- -- output signals
-- cmd_ack : out std_logic;
-- ack_out : out std_logic;
-- i2c_busy : out std_logic;
-- i2c_al : out std_logic;
-- dout : out std_logic_vector(7 downto 0);
--
-- -- i2c lines
-- scl_i : in std_logic; -- i2c clock line input
-- scl_o : out std_logic; -- i2c clock line output
-- scl_oen : out std_logic; -- i2c clock line output enable, active low
-- sda_i : in std_logic; -- i2c data line input
-- sda_o : out std_logic; -- i2c data line output
-- sda_oen : out std_logic -- i2c data line output enable, active low
-- );
-- end component i2c_master_byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- internal reset signal
signal rst_i : std_logic;
-- wishbone write access
signal wb_wacc : std_logic;
-- internal acknowledge signal
signal iack_o : std_logic;
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
signal core_en : std_logic; -- core enable signal
signal ien : std_logic; -- interrupt enable signal
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- i2c bus busy (start signal detected)
signal i2c_al, al : std_logic; -- arbitration lost
begin
-- generate internal reset signal
rst_i <= arst_i xor ARST_LVL;
-- generate acknowledge output signal
gen_ack_o : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored
end if;
end process gen_ack_o;
wb_ack_o <= iack_o;
-- generate wishbone write access signal
wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
-- assign wb_dat_o
assign_dato : process(wb_clk_i)
begin
if (wb_clk_i'event and wb_clk_i = '1') then
if (wb_stb_i = '1' and wb_we_i = '0') then
case wb_adr_i is
when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8));
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr; -- write is transmit register TxR
when "100" => wb_dat_o <= sr; -- write is command register CR
-- Debugging registers:
-- These registers are not documented.
-- Functionality could change in future releases
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= x"23"; --(others => '0');
when others => wb_dat_o <= (others => 'X'); -- for simulation only
end case;
else
wb_dat_o <= (others => '0');
end if;
end if;
end process assign_dato;
-- generate registers (CR, SR see below)
gen_regs: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case wb_adr_i is
when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
when "010" => ctr <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when "100" => null; --write to CR, avoid executing the others clause
-- illegal cases, for simulation only
when others =>
report ("Illegal write address, setting all registers to unknown.");
prer <= (others => 'X');
ctr <= (others => 'X');
txr <= (others => 'X');
end case;
end if;
end if;
end process gen_regs;
-- generate command register
gen_cr: process(rst_i, wb_clk_i)
begin
if (rst_i = '0') then
cr <= (others => '0');
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
cr <= (others => '0');
elsif (wb_wacc = '1') then
if ( (core_en = '1') and (wb_adr_i = 4) ) then
-- only take new commands when i2c core enabled
-- pending commands are finished
cr <= wb_dat_i;
end if;
else
if (done = '1' or i2c_al = '1') then
cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
end if;
cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0'
cr(0) <= '0'; -- clear IRQ_ACK bit
end if;
end if;
end process gen_cr;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
ien <= ctr(6);
-- hookup byte controller block
byte_ctrl: entity work.i2c_master_byte_ctrl port map (
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
i2c_al => i2c_al,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o
);
-- status register block + interrupt request signal
st_irq_block : block
begin
-- generate status register bits
gen_sr_bits: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al or (al and not sta);
rxack <= irxack;
tip <= (rd or wr);
-- interrupt request flag is always generated
irq_flag <= (done or i2c_al or irq_flag) and not iack;
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (wb_clk_i, rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif (wb_clk_i'event and wb_clk_i = '1') then
if (wb_rst_i = '1') then
wb_inta_o <= '0';
else
-- interrupt signal is only generated when IEN (interrupt enable bit) is set
wb_inta_o <= irq_flag and ien;
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_wrapper is
generic ( prescale : std_logic_vector(15 downto 0) := x"00c8");
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector(15 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
debug : out std_logic_vector(3 downto 0)
);
end;
architecture i2c_wrapper of i2c_wrapper is
signal wb_adr : unsigned(2 downto 0);
signal wb_dati : std_logic_vector(7 downto 0);
signal wb_dato : std_logic_vector(7 downto 0);
signal wb_we : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_ack : std_logic;
signal wb_inta : std_logic;
signal wb_dat_oq : std_logic_vector(7 downto 0);
signal cnt : unsigned(3 downto 0);
signal wb_dowrite : std_logic;
signal wb_doread : std_logic;
signal end_cnt : integer range 0 to 11;
type i2c_rec is record
adr : unsigned(2 downto 0);
dat : std_logic_vector(7 downto 0);
int : std_logic;
end record;
type i2c_mem is ARRAY(0 to 11) of i2c_rec;
signal dat : i2c_mem;
type i2c_states is (IDLE, I2C_GO, I2C_WAIT_INT, I2C_GET_RXDAT, I2C_WB_ACK);
signal i2c_sm : i2c_states;
signal scl : std_logic;
signal sda : std_logic;
signal scl_oen : std_logic;
signal sda_oen : std_logic;
signal i2c_init_done : std_logic;
begin
scl_o <= scl when scl_oen = '0' else '1';
sda_o <= sda when sda_oen = '0' else '1';
wb_dat_o <= wb_dat_oq;
i2c_master : entity work.i2c_master_top
generic map( ARST_LVL => '1' )
port map (
-- wishbone signals
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
arst_i => wb_rst_i,
wb_adr_i => std_logic_vector(wb_adr),
wb_dat_i => wb_dati,
wb_dat_o => wb_dato,
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc,
wb_ack_o => wb_ack,
wb_inta_o => wb_inta,
-- i2c lines
scl_pad_i => scl_i,
scl_pad_o => scl,
scl_padoen_o => scl_oen,
sda_pad_i => sda_i,
sda_pad_o => sda,
sda_padoen_o => sda_oen
);
i2c_write: process (wb_clk_i, wb_rst_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
wb_dat_oq <= (others => '0');
cnt <= (others => '0');
i2c_init_done <= '0';
wb_dowrite <= '0';
wb_doread <= '0';
end_cnt <= 0;
else
dat <= dat;
if wb_ack = '1' and i2c_sm = I2C_GO then
cnt <= cnt + "1";
elsif i2c_sm = IDLE and i2c_init_done = '1' then
cnt <= "0011";
elsif i2c_sm = IDLE and i2c_init_done = '0' then
cnt <= "0000";
end if;
if i2c_sm = IDLE and wb_stb_i = '1' then
if wb_we_i = '1' then
-- PRESCALE Register enable core and interrupt
dat <= (("000", prescale(7 downto 0),'0'), ("001", prescale(15 downto 8),'0'), ("010", x"c0",'0'),
-- ADDRESS STA and WR bit DATA/REG STA and WR
("011", x"EC", '0'), ("100", x"90",'1'), ("011", x"ff", '0'), ("100", x"90",'1'),
-- DATA STO and WR
("011", x"ff",'0'), ("100", x"50", '1'));
dat(3).dat <= wb_adr_i(15 downto 0);
dat(5).dat <= wb_adr_i( 7 downto 0);
dat(8).dat <= wb_dat_i;
end_cnt <= 9;
else
dat <= (("000", prescale(7 downto 0),'0'), ("001", prescale(15 downto 8),'0'), ("010", x"c0",'0'),
-- ADDRESS STA and WR bit DATA/REG WR
("011", x"EC", '0'), ("100", x"91",'1'), ("011", x"ff", '0'), ("100", x"11", '1'),
-- ADDRESS STA,WR STO, RD, NACK
("011", x"ED", '0'), ("100", x"91",'1'), ("100", x"69", '1'), ("111", x"00", '0'), ("111", x"00", '0'));
dat(3).dat <= wb_adr_i(15 downto 9) & '0'; -- address write
dat(5).dat <= wb_adr_i( 7 downto 0); -- memory location
dat(7).dat <= wb_adr_i(15 downto 9) & '1'; -- address read
end_cnt <= 10;
end if;
end if;
i2c_init_done <= i2c_init_done;
if i2c_sm = I2C_GO and cnt = "0010" then
i2c_init_done <= '1';
end if;
if i2c_sm = I2C_GET_RXDAT and wb_ack = '1' then
wb_dat_oq <= wb_dato;
end if;
case i2c_sm is
when IDLE =>
if (wb_stb_i = '1') then
i2c_sm <= I2C_GO;
end if;
when I2C_GO =>
wb_dowrite <= '1';
if wb_ack = '1' and dat(to_integer(cnt)).int = '1' then
i2c_sm <= I2C_WAIT_INT;
wb_dowrite <= '0';
elsif wb_ack = '1' and dat(to_integer(cnt)).int = '0' then
if to_integer(cnt) = end_cnt then
i2c_sm <= I2C_GET_RXDAT;
end if;
wb_dowrite <= '0';
end if;
when I2C_WAIT_INT =>
wb_doread <= '1';
if wb_ack = '1' and wb_dato(1) = '0' then
wb_doread <= '0';
if to_integer(cnt) = end_cnt then
i2c_sm <= I2C_GET_RXDAT;
else
i2c_sm <= I2C_GO;
end if;
end if;
when I2C_GET_RXDAT =>
wb_doread <= '1';
if wb_ack = '1' then
wb_doread <= '0';
i2c_sm <= I2C_WB_ACK;
end if;
when I2C_WB_ACK =>
i2c_sm <= IDLE;
end case;
end if;
end if;
end process;
wb_ack_o <= '1' when i2c_sm = I2C_WB_ACK else '0';
wb_dati <= dat(to_integer(cnt)).dat;
wb_adr <= dat(to_integer(cnt)).adr when wb_dowrite = '1' else
"011" when i2c_sm = I2C_GET_RXDAT else
"100";
wb_cyc <= wb_stb;
wb_stb <= '1' when (wb_dowrite = '1' or wb_doread = '1') and wb_ack = '0' else '0';
wb_we <= wb_dowrite;
debug(3 downto 0) <= std_logic_vector(cnt);
end i2c_wrapper;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sim_tb is
end sim_tb;
architecture rtl of sim_tb is
constant CLK_PERIOD : time := 10 ns;
signal clk : std_logic;
signal rst : std_logic;
signal rst_n : std_logic;
component i2c_wrapper is
generic ( prescale : std_logic_vector(15 downto 0) := x"00c8");
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
wb_adr_i : in std_logic_vector(15 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_ack_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
debug : out std_logic_vector(3 downto 0)
);
end component;
component i2c_rom is
port (
clk : in std_logic;
rst_n : in std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_i : in std_logic
);
end component;
signal wb_clk_i : std_logic;
signal wb_rst_i : std_logic;
signal wb_adr_i : std_logic_vector(15 downto 0);
signal wb_dat_i : std_logic_vector(7 downto 0);
signal wb_dat_o : std_logic_vector(7 downto 0);
signal wb_we_i : std_logic;
signal wb_stb_i : std_logic;
signal wb_ack_o : std_logic;
signal scl_wi : std_logic;
signal scl_wo : std_logic;
signal sda_wi : std_logic;
signal sda_wo : std_logic;
signal debug : std_logic_vector(3 downto 0);
signal sda_ro : std_logic;
begin
rst <= transport '1', '0' after (4 * CLK_PERIOD);
rst_n <= not rst;
clock: process begin
clk <= '1', '0' after CLK_PERIOD/2;
wait for CLK_PERIOD;
end process;
wb_clk_i <= clk;
wb_rst_i <= rst;
beh_mst: process
begin
wb_dat_i <= x"00";
wb_we_i <= '0';
wb_adr_i <= x"6a08";
wb_stb_i <= '0';
wait for 20*CLK_PERIOD;
wb_stb_i <= '1';
wait until wb_ack_o = '1';
wb_stb_i <= '0';
wait;
end process beh_mst;
DUT_MST: i2c_wrapper
port map (
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_ack_o => wb_ack_o,
scl_i => scl_wi,
scl_o => scl_wo,
sda_i => sda_wi,
sda_o => sda_wo
);
scl_wi <= scl_wo;
sda_wi <= '1' when sda_ro = 'Z' else
'0' when sda_ro = '0' else sda_wo;
DUT: i2c_rom
port map (
clk => wb_clk_i,
rst_n => rst_n,
sda_i => sda_wo,
sda_o => sda_ro,
scl_i => scl_wo
);
end rtl;

256
fpga/src/i2c/slave/hdmi_in.dat Normal file
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@@ -0,0 +1,256 @@
00
ff
ff
ff
ff
ff
ff
00
4d
29
58
47
00
00
00
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14
01
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80
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0d
78
07
0d
c2
a0
57
47
98
27
12
48
4f
00
00
00
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
06
18
a0
dd
50
1c
22
20
51
3c
82
04
26
71
10
00
00
18
00
00
00
fe
00
48
44
4d
49
49
4e
0a
20
20
20
20
20
20
2e
18
a0
dd
50
1c
22
20
51
3c
82
04
27
71
10
00
00
18
00
00
00
fa
00
01
00
01
00
01
00
01
00
01
00
01
00
0a
00
0e
02
03
04
00
00
00
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f7

128
fpga/src/i2c/slave/hdmi_in_syncmaster191t.dat Normal file
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@@ -0,0 +1,128 @@
00
ff
ff
ff
ff
ff
ff
00
4c
2d
14
00
39
31
48
47
0d
0d
01
03
80
26
1f
8c
2a
6f
8b
a2
5a
4d
94
24
1a
51
56
bf
ef
80
81
80
61
40
45
40
31
40
01
01
01
01
01
01
01
01
30
2a
00
98
51
00
2a
40
30
70
13
00
78
2d
11
00
00
1e
00
00
00
fd
00
38
55
1e
51
0d
00
0a
20
20
20
20
20
20
00
00
00
fc
00
53
79
6e
63
4d
61
73
74
65
72
0a
20
20
00
00
00
ff
00
48
4a
47
57
33
30
33
34
33
33
0a
20
20
00
61

256
fpga/src/i2c/slave/hdmi_in_syncmaster940t.dat Normal file
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@@ -0,0 +1,256 @@
00
ff
ff
ff
ff
ff
ff
00
4c
2d
bb
01
39
31
41
48
14
11
01
03
80
26
1e
78
2a
de
95
a3
54
4c
99
26
0f
50
54
bf
ef
80
81
80
81
40
71
4f
01
01
01
01
01
01
01
01
01
01
30
2a
00
98
51
00
2a
40
30
70
13
00
78
2d
11
00
00
1e
00
00
00
fd
00
38
4b
1e
51
0e
00
0a
20
20
20
20
20
20
00
00
00
fc
00
53
79
6e
63
4d
61
73
74
65
72
0a
20
20
00
00
00
ff
00
48
4d
45
50
35
31
31
34
30
32
0a
20
20
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83
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00

80
fpga/src/i2c/slave/i2c_rom.vhd Normal file
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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity i2c_rom is
port (
clk : in std_logic;
rst_n : in std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_i : in std_logic
);
end i2c_rom;
architecture i2c_rom of i2c_rom is
--type rom_t is array (0 to 255) of std_logic_vector (7 downto 0);
type rom_t is array (0 to 127) of std_logic_vector (7 downto 0);
impure function init_rom_from_file(filename : in string) return rom_t is
file romfile : text is in filename;
variable rline : line;
variable rom : rom_t;
begin
for i in rom_t'range loop
readline(romfile, rline);
hread(rline, rom(i));
end loop;
return rom;
end function;
--signal rom : rom_t := init_rom_from_file("hdmi_in_syncmaster940t.dat");
signal rom : rom_t := init_rom_from_file("hdmi_in_syncmaster191t.dat");
signal rd_data : std_logic_vector(7 downto 0);
signal wr_data : std_logic_vector(7 downto 0);
signal address : std_logic_vector(7 downto 0);
signal wr_pulse : std_logic;
signal rd_pulse : std_logic;
signal rd_wr : std_logic;
begin
rd_data <= rom(to_integer(unsigned(address)));
i2c_blk_0: entity work.i2c_slave
generic map ( ADDRESS => "0101000" ) -- 6A write, 6B read
port map (
clk => clk,
rst_n => rst_n,
sda_i => sda_i,
sda_o => sda_o,
scl_i => scl_i,
rd_dat_i => rd_data,
addr_o => address,
wr_dat_o => wr_data,
wr_pulse_o => wr_pulse,
rd_pulse_o => rd_pulse,
rd_wr_o => rd_wr
);
end i2c_rom;

282
fpga/src/i2c/slave/i2c_slave.vhd Normal file
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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
-- Verilog to VHDL translation of:
-- http://www.eda365.com/thread-31086-1-1.html
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic (ADDRESS : std_logic_vector(6 downto 0) := "0110101"); -- 6A write, 6B read
port (
clk : in std_logic;
rst_n : in std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_i : in std_logic;
rd_dat_i : in std_logic_vector(7 downto 0);
addr_o : out std_logic_vector(7 downto 0);
wr_dat_o : out std_logic_vector(7 downto 0);
wr_pulse_o : out std_logic;
rd_pulse_o : out std_logic;
rd_wr_o : out std_logic
);
end i2c_slave;
architecture i2c_slave of i2c_slave is
signal sda_sr : std_logic_vector(3 downto 0);
signal scl_sr : std_logic_vector(3 downto 0);
signal sda, was_sda : std_logic;
signal sda_in : std_logic;
signal scl, was_scl : std_logic;
signal scl_in : std_logic;
signal i2c_start : std_logic;
signal i2c_stop : std_logic;
signal ack_cyc : std_logic;
signal byte_count : unsigned(3 downto 0);
signal was_ack : std_logic;
signal addr_byte : std_logic;
signal addr_ack : std_logic;
signal subad_byte : std_logic;
signal subad_ack : std_logic;
signal wr_pulse : std_logic;
signal rd_pulse : std_logic;
signal rd_wr : std_logic;
signal wr_dat : std_logic_vector(7 downto 0);
signal addr : unsigned(7 downto 0);
signal out_sr : std_logic_vector(7 downto 0);
signal in_sr : std_logic_vector(7 downto 0);
signal wr_pls_dly : std_logic;
signal rd_pls_dly : std_logic;
signal drive_sda : std_logic;
signal my_cyc : std_logic;
signal data_byte : std_logic;
begin
wr_dat_o <= wr_dat;
addr_o <= std_logic_vector(addr);
rd_wr_o <= rd_wr;
wr_pulse_o <= wr_pulse;
rd_pulse_o <= rd_pulse;
sda_o <= '0' when drive_sda = '1' else '1';
-- Debounce, then delay debounced signals for edge detection
debounce: process (clk, rst_n)
begin
if rst_n = '0' then
sda_sr <= "1111"; -- Start up assuming quiescent state of inputs
sda <= '1';
was_sda <= '0';
scl_sr <= "1111"; -- Start up assuming quiescent state of inputs
scl <= '1';
was_scl <= '0';
sda_in <= '1';
elsif rising_edge(clk) then
sda_in <= sda_i;
scl_in <= scl_i;
sda_sr <= sda_sr(2 downto 0) & sda_in;
if sda_sr = "0000" then
sda <= '0';
elsif sda_sr = "1111" then
sda <= '1';
end if;
was_sda <= sda;
scl_sr <= scl_sr(2 downto 0) & scl_in;
if scl_sr = "0000" then
scl <= '0';
elsif scl_sr = "1111" then
scl <= '1';
end if;
was_scl <= scl;
end if;
end process;
ack_cyc <= byte_count(3);
process (clk, rst_n)
begin
if rst_n = '0' then
i2c_start <= '0';
i2c_stop <= '0';
byte_count <= (others => '0');
was_ack <= '0';
addr_byte <= '0';
addr_ack <= '0';
subad_byte <= '0';
subad_ack <= '0';
wr_pulse <= '0';
rd_pulse <= '0';
wr_dat <= (others => '0');
addr <= (others => '0');
out_sr <= (others => '1');
in_sr <= (others => '0');
wr_pls_dly <= '0';
rd_pls_dly <= '0';
rd_wr <= '0';
drive_sda <= '0';
my_cyc <= '0';
elsif rising_edge(clk) then
-- Falling edge of SDA with SCL high
if scl = '1' and was_scl = '1' and sda = '0' and was_sda = '1' then
i2c_start <= '1';
elsif scl = '0' and was_scl = '0' then -- Hold until SCL has fallen
i2c_start <= '0';
end if;
-- Rising edge of SDA with SCL high
-- i2c_stop is only on for one clock cycle
i2c_stop <= scl and was_scl and sda and not was_sda;
-- Increment bit counter on falling edges of the
-- SCL signal after the first in a packet.
-- Count bit position within bytes:
if i2c_start = '1' then
byte_count <= (others => '0');
elsif scl = '0' and was_scl = '1' and i2c_start = '0' then
if ack_cyc = '1' then
byte_count <= (others => '0');
else
byte_count <= byte_count + "1";
end if;
end if;
-- For edge detection of ack cycles:
was_ack <= ack_cyc;
-- addr_byte is on during the first byte transmitted after
-- a START condition.
if i2c_start = '1' then
addr_byte <= '1';
elsif ack_cyc = '1' then
addr_byte <= '0';
end if;
-- addr_ack is on during acknowledge cycle of the address
-- byte.
if addr_byte = '1' and ack_cyc = '1' then
addr_ack <= '1';
elsif ack_cyc = '0' then
addr_ack <= '0';
end if;
-- subad_byte is on for the second byte of my write cycle.
if addr_ack = '1' and ack_cyc = '0' and rd_wr = '0' and my_cyc = '1' then
subad_byte <= '1';
elsif ack_cyc = '1' then
subad_byte <= '0';
end if;
-- subad_ack is on during the acknowledge cycle of the
-- subaddress byte.
if subad_byte = '1' and ack_cyc = '1' then
subad_ack <= '1';
elsif ack_cyc = '0' then
subad_ack <= '0';
end if;
-- data_byte is on for my read or write data cycles. This is
-- any read cycle after the address, or write cycles after
-- the subaddress. It remains on until the I2C STOP event or
-- any NACK.
if (addr_ack = '1' and ack_cyc = '0' and rd_wr = '1' and my_cyc = '1')
or (subad_ack = '1' and ack_cyc = '0') then
data_byte <= '1';
elsif i2c_stop = '1' or (ack_cyc = '1' and scl = '1' and sda = '1') then
data_byte <= '0';
end if;
-- wr_pulse_o is on for one clock cycle while the data
-- on the output bus is valid.
wr_pulse <= data_byte and not ack_cyc and was_ack and not rd_wr;
-- rd_pulse_o is on for one clock cycle when external
-- read data is transfered into the output shift register
-- for transmission to the I2C bus.
rd_pulse <= (addr_ack and not ack_cyc and rd_wr and my_cyc) -- First read cycle
or (data_byte and not ack_cyc and was_ack and rd_wr); -- Subsequent read cycles
-- wr_dat_o is loaded from the I2C input S/R at the
-- end of each write data cycle.
if data_byte = '1' and ack_cyc = '1' and was_ack = '0' and rd_wr = '0' then
wr_dat <= in_sr;
end if;
-- out_sr shifts data out to the I2C bus during read
-- data cycles. Transitions occur after the falling
-- edge of SCL. Fills with 1's from right.
if rd_pulse = '1' then
out_sr <= rd_dat_i;
elsif scl = '0' and was_scl = '1' then
out_sr <= out_sr(6 downto 0) & '1';
end if;
-- Delayed pulses for incrementing subaddress:
wr_pls_dly <= wr_pulse;
rd_pls_dly <= rd_pulse;
-- addr_o is loaded after the second byte of a write
-- cycle has fully shifted in. It increments after each
-- read or write access.
if subad_byte = '1' and ack_cyc = '1' then
addr <= unsigned(in_sr);
elsif wr_pls_dly = '1' or rd_pls_dly = '1' then
-- Leave Out this else clause for simple single register version
-- In this case addr_o becomes the register output and should be
-- wrapped back to rd_dat_i externally
addr <= addr + "1";
end if;
-- Shift I2C data in after rising edge of SCL.
if scl = '1' and was_scl = '0' then
in_sr <= in_sr(6 downto 0) & sda;
end if;
-- Read / not Write. For external bus drivers if necessary.
-- Latch the Read bit of the address cycle.
if addr_byte = '1' and ack_cyc = '1' then
rd_wr <= in_sr(0);
end if;
-- Decode address. My cycle if address upper 7 bits
-- match with i2c_address defined above.
if i2c_start = '1' then
my_cyc <= '0'; --- ??!?!?
elsif addr_byte = '1' and ack_cyc = '1' then
if in_sr(7 downto 1) = ADDRESS then
my_cyc <= '1';
else
my_cyc <= '1';
end if;
end if;
-- I2C data output drive low signal (1 = drive SDA low)
-- Invert this signal for T input of OBUFT or IOBUF
-- or use it directly for OBUFE.
drive_sda <= (my_cyc and addr_ack) -- Address acknowledge
or (my_cyc and not rd_wr and ack_cyc) -- Write byte acknowledge
or (data_byte and rd_wr and not ack_cyc and not out_sr(7)); -- Read Data
end if;
end process;
end i2c_slave;

194
fpga/src/sig/ddr2dvi.vhd Normal file
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@@ -0,0 +1,194 @@
-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dvi_package.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ddr2dvi is
port (
clk : in std_logic;
rst_n : in std_logic;
rst_pll : in std_logic;
tx_tmds : out std_logic_vector(3 downto 0);
tx_tmds_n : out std_logic_vector(3 downto 0);
tx_pll_locked_o : out std_logic;
-- memory interface
ddr2_cmd_en_o : out std_logic;
ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
ddr2_cmd_empty_i : in std_logic;
ddr2_cmd_full_i : in std_logic;
ddr2_rd_en_o : out std_logic;
ddr2_rd_data_i : in std_logic_vector(31 downto 0);
ddr2_rd_full_i : in std_logic;
ddr2_rd_empty_i : in std_logic;
ddr2_rd_count_i : in std_logic_vector( 6 downto 0);
ddr2_rd_overflow_i : in std_logic;
ddr2_rd_error_i : in std_logic
);
end ddr2dvi;
architecture ddr2dvi of ddr2dvi is
signal pclk : std_logic;
signal pclk_buf : std_logic;
signal tx_hsync : std_logic;
signal tx_vsync : std_logic;
signal tx_color_en : std_logic;
signal tx_color : color_t(COLOR_CNT-1 downto 0);
signal tx_pclkx2 : std_logic;
signal tx_pclkx10 : std_logic;
signal tx_reset_n : std_logic;
signal tx_serdesstrobe : std_logic;
signal tx_clkfbout : std_logic;
signal tx_clkfbin : std_logic;
signal tx_plllckd : std_logic;
signal tx_pllclk0 : std_logic;
signal tx_pllclk2 : std_logic;
signal tx_bufpll_lock : std_logic;
begin
tx_pll_locked_o <= tx_plllckd;
-- ----------------------------------------------------------------------------
-- DDR2 READ Signal Generator
-- ----------------------------------------------------------------------------
sig_read_0: entity work.sig_read
generic map (
MEM_START_ADR => "00" & x"0000000",
H_ACTIVE_PIXEL => x"500",
H_BLANKING => x"198",
H_SYNC_WIDTH => x"070",
H_SYNC_OFFSET => x"030",
V_ACTIVE_LINES => x"400",
V_BLANKING => x"02a",
V_SYNC_WIDTH => x"01",
V_SYNC_OFFSET => x"03"
)
port map (
clk => pclk,
rst_n => rst_n,
-- memory interface
ddr2_clk => clk,
ddr2_cmd_en_o => ddr2_cmd_en_o,
ddr2_cmd_instr_o => ddr2_cmd_instr_o,
ddr2_cmd_bl_o => ddr2_cmd_bl_o,
ddr2_cmd_byte_addr_o => ddr2_cmd_byte_addr_o,
ddr2_cmd_empty_i => ddr2_cmd_empty_i,
ddr2_cmd_full_i => ddr2_cmd_full_i,
ddr2_rd_en_o => ddr2_rd_en_o,
ddr2_rd_data_i => ddr2_rd_data_i,
ddr2_rd_full_i => ddr2_rd_full_i,
ddr2_rd_empty_i => ddr2_rd_empty_i,
ddr2_rd_count_i => ddr2_rd_count_i,
ddr2_rd_overflow_i => ddr2_rd_overflow_i,
ddr2_rd_error_i => ddr2_rd_error_i,
en_stb_i => '1',
hsync_o => tx_hsync,
vsync_o => tx_vsync,
color_en_o => tx_color_en,
color_o => tx_color
);
-- ----------------------------------------------------------------------------
-- Instantiate a dedicate PLL for output port
-- ----------------------------------------------------------------------------
--pclk <= ddr2_clk_out;
pll_oserdes_0: PLL_BASE
generic map (
CLKIN_PERIOD => 9.0,
CLKFBOUT_MULT => 29, --10 --set VCO to 10x of CLKIN
DIVCLK_DIVIDE => 3,
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 10,
CLKOUT2_DIVIDE => 5,
COMPENSATION => "SOURCE_SYNCHRONOUS"
)
port map (
CLKFBOUT => tx_clkfbout,
CLKOUT0 => tx_pllclk0,
CLKOUT1 => pclk_buf,
CLKOUT2 => tx_pllclk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => tx_plllckd,
CLKFBIN => tx_clkfbin,
CLKIN => clk,
RST => rst_pll
);
pclk_buf_0: BUFG port map(I => pclk_buf, O => pclk);
-- ----------------------------------------------------------------------------
-- This BUFG is needed in order to deskew between PLL clkin and clkout
-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
-- ----------------------------------------------------------------------------
tx_clkfb_buf: BUFG port map(I => tx_clkfbout, O => tx_clkfbin);
-- --------------------------------
-- regenerate pclkx2 for TX
-- --------------------------------
tx_pclkx2_buf: BUFG port map(I => tx_pllclk2, O => tx_pclkx2);
-- --------------------------------
-- regenerate pclkx10 for TX
-- --------------------------------
tx_ioclk_buf: BUFPLL
generic map ( DIVIDE => 5 )
port map (
PLLIN => tx_pllclk0,
GCLK => tx_pclkx2,
LOCKED => tx_plllckd,
IOCLK => tx_pclkx10,
SERDESSTROBE => tx_serdesstrobe,
LOCK => tx_bufpll_lock
);
tx_reset_n <= tx_bufpll_lock;
dvi_encoder_0: entity work.dvi_encoder
port map (
rst_n => tx_reset_n,
pclk => pclk,
pclkx2 => tx_pclkx2,
pclkx10 => tx_pclkx10,
serdesstrobe_i => tx_serdesstrobe,
color_i => tx_color,
hsync_i => tx_hsync,
vsync_i => tx_vsync,
dat_en_i => tx_color_en,
tmds_p => tx_tmds,
tmds_n => tx_tmds_n
);
end ddr2dvi;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dvi_package.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dvi2ddr is
port (
clk : in std_logic;
rst : in std_logic;
ctrl_disable_wr : in std_logic;
rx_tmds : in std_logic_vector(3 downto 0);
rx_tmds_n : in std_logic_vector(3 downto 0);
-- memory interface
ddr2_cmd_en_o : out std_logic;
ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
ddr2_cmd_empty_i : in std_logic;
ddr2_cmd_full_i : in std_logic;
ddr2_wr_en_o : out std_logic;
ddr2_wr_mask_o : out std_logic_vector( 3 downto 0);
ddr2_wr_data_o : out std_logic_vector(31 downto 0);
ddr2_wr_full_i : in std_logic;
ddr2_wr_empty_i : in std_logic;
ddr2_wr_count_i : in std_logic_vector( 6 downto 0);
ddr2_wr_underrun_i : in std_logic;
ddr2_wr_error_i : in std_logic
);
end dvi2ddr;
architecture dvi2ddr of dvi2ddr is
signal rx_tmds_s : std_logic_vector(3 downto 0);
signal rx_color : color_t(COLOR_CNT-1 downto 0);
signal rx_color_en : std_logic;
signal rx_pll_lckd : std_logic;
signal rx_rst_n : std_logic;
signal rx_pclk : std_logic;
signal rx_hsync : std_logic;
signal rx_vsync : std_logic;
begin
-- ----------------------------------------------------------------------------
-- HDMI to DDR2
-- ----------------------------------------------------------------------------
dvi_decoder_0: entity work.dvi_decoder
port map (
ext_rst => rst,
tmdsclk_p => rx_tmds(3),
tmdsclk_n => rx_tmds_n(3),
din_p => rx_tmds(2 downto 0),
din_n => rx_tmds_n(2 downto 0),
reset_n => rx_rst_n, -- rx reset
pclk_o => rx_pclk, -- regenerated pixel clock
pclkx2_o => open, -- double rate pixel clock
pclkx10_o => open, -- 10x pixel as IOCLK
pll_lckd_o => rx_pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL
serdesstrobe_o => open, -- BUFPLL serdesstrobe output
tmdsclk_o => open, -- TMDS cable clock
hsync_o => rx_hsync, -- hsync data
vsync_o => rx_vsync, -- vsync data
valid_o => open,
ready_o => open,
psalgnerr_o => open,
sdout_o => open,
dat_en_o => rx_color_en, -- data enable
color_o => rx_color
);
sig_write_0: entity work.sig_write
generic map (MEM_START_ADR => "00" & x"0000000")
port map (
clk => rx_pclk,
rst_n => rx_rst_n,
ctrl_disable_wr => ctrl_disable_wr,
-- memory interface
ddr2_clk => clk,
ddr2_cmd_en_o => ddr2_cmd_en_o,
ddr2_cmd_instr_o => ddr2_cmd_instr_o,
ddr2_cmd_bl_o => ddr2_cmd_bl_o,
ddr2_cmd_byte_addr_o => ddr2_cmd_byte_addr_o,
ddr2_cmd_empty_i => ddr2_cmd_empty_i,
ddr2_cmd_full_i => ddr2_cmd_full_i,
ddr2_wr_en_o => ddr2_wr_en_o,
ddr2_wr_mask_o => ddr2_wr_mask_o,
ddr2_wr_data_o => ddr2_wr_data_o,
ddr2_wr_full_i => ddr2_wr_full_i,
ddr2_wr_empty_i => ddr2_wr_empty_i,
ddr2_wr_count_i => ddr2_wr_count_i,
ddr2_wr_underrun_i => ddr2_wr_underrun_i,
ddr2_wr_error_i => ddr2_wr_error_i,
-- display output
hsync_i => rx_hsync,
vsync_i => rx_vsync,
color_en_i => rx_color_en,
color_i => rx_color
);
end dvi2ddr;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
entity sig is
generic (
H_ACTIVE_PIXEL : unsigned(11 downto 0) := x"5a0";
H_BLANKING : unsigned(11 downto 0) := x"0dd";
H_SYNC_WIDTH : unsigned(11 downto 0) := x"03c";
H_SYNC_OFFSET : unsigned(11 downto 0) := x"050"; -- front porch
V_ACTIVE_LINES : unsigned(11 downto 0) := x"21c";
V_BLANKING : unsigned(11 downto 0) := x"022";
V_SYNC_WIDTH : unsigned( 7 downto 0) := x"02";
V_SYNC_OFFSET : unsigned( 7 downto 0) := x"18" -- front porch
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- memory interface
--address_o : out std_logic_vector();
-- display output
en_stb_i : in std_logic;
hsync_o : out std_logic;
vsync_o : out std_logic;
color_en_o : out std_logic;
color_o : out color_t
);
end sig;
architecture sig of sig is
signal h_cnt : unsigned(11 downto 0);
signal v_cnt : unsigned(11 downto 0);
signal one_screen : std_logic;
signal h_state : unsigned(1 downto 0);
signal h_state_i : unsigned(1 downto 0);
signal v_state : unsigned(1 downto 0);
signal v_state_i : unsigned(1 downto 0);
constant SYNC_OFF : unsigned(1 downto 0) := "00";
constant SYNC : unsigned(1 downto 0) := "01";
constant SYNC_BACK : unsigned(1 downto 0) := "10";
constant ACTIVE_LINE : unsigned(1 downto 0) := "11";
constant H_SYNC_BACK : unsigned(11 downto 0) := H_BLANKING - H_SYNC_OFFSET - H_SYNC_WIDTH;
constant V_SYNC_BACK : unsigned(11 downto 0) := V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH;
begin
hsync_o <= '1' when h_state = SYNC and v_state = ACTIVE_LINE else '0';
vsync_o <= '1' when v_state = SYNC else '0';
color_en_o <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
color_o <= ((others => v_cnt(3)), (others => v_cnt(2)), (others => v_cnt(1)));
process (clk, rst_n)
begin
if rst_n = '0' then
h_cnt <= x"000";
v_cnt <= x"000";
v_state <= "00";
v_state_i <= "00";
h_state <= "00";
h_state_i <= "00";
one_screen <= '0';
elsif rising_edge(clk) then
if v_state = ACTIVE_LINE and v_cnt = x"000" then
one_screen <= '0';
elsif en_stb_i = '1' then
one_screen <= '1';
end if;
if one_screen = '1' and h_cnt = x"000" then
h_state <= h_state_i;
case h_state_i is
when SYNC_OFF => h_cnt <= H_SYNC_OFFSET-1;
when SYNC => h_cnt <= H_SYNC_WIDTH-1;
when SYNC_BACK => h_cnt <= H_SYNC_BACK-1;
when ACTIVE_LINE => h_cnt <= H_ACTIVE_PIXEL-1;
when others => h_cnt <= x"000";
end case;
elsif h_cnt /= x"000" then
h_cnt <= h_cnt - "1";
end if;
if one_screen = '1' and h_cnt = x"000" then
h_state_i <= h_state_i + "01";
end if;
if one_screen = '1' and v_cnt = x"000" and h_state = SYNC_OFF then
v_state <= v_state_i;
case v_state_i is
when SYNC_OFF => v_cnt <= x"0" & V_SYNC_OFFSET;
when SYNC => v_cnt <= x"0" & V_SYNC_WIDTH;
when SYNC_BACK => v_cnt <= V_SYNC_BACK;
when ACTIVE_LINE => v_cnt <= V_ACTIVE_LINES;
when others => v_cnt <= x"000";
end case;
elsif v_cnt /= x"000" and (h_state = ACTIVE_LINE and h_cnt = x"000") then
v_cnt <= v_cnt - "1";
end if;
if one_screen = '1' and v_cnt = x"000" then
v_state_i <= v_state_i + "01";
end if;
end if;
end process;
end sig;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
entity sig_read is
generic (
MEM_START_ADR : unsigned(29 downto 0) := "00" & x"0000000";
H_ACTIVE_PIXEL : unsigned(11 downto 0) := x"5a0";
H_BLANKING : unsigned(11 downto 0) := x"0dd";
H_SYNC_WIDTH : unsigned(11 downto 0) := x"03c";
H_SYNC_OFFSET : unsigned(11 downto 0) := x"050"; -- front porch
V_ACTIVE_LINES : unsigned(11 downto 0) := x"21c";
V_BLANKING : unsigned(11 downto 0) := x"022";
V_SYNC_WIDTH : unsigned( 7 downto 0) := x"02";
V_SYNC_OFFSET : unsigned( 7 downto 0) := x"18" -- front porch
);
port (
clk : in std_logic;
rst_n : in std_logic;
-- memory interface
ddr2_clk : in std_logic;
ddr2_cmd_en_o : out std_logic;
ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
ddr2_cmd_empty_i : in std_logic;
ddr2_cmd_full_i : in std_logic;
ddr2_rd_en_o : out std_logic;
ddr2_rd_data_i : in std_logic_vector(31 downto 0);
ddr2_rd_full_i : in std_logic;
ddr2_rd_empty_i : in std_logic;
ddr2_rd_count_i : in std_logic_vector( 6 downto 0);
ddr2_rd_overflow_i : in std_logic;
ddr2_rd_error_i : in std_logic;
-- display output
en_stb_i : in std_logic;
hsync_o : out std_logic;
vsync_o : out std_logic;
color_en_o : out std_logic;
color_o : out color_t(COLOR_CNT-1 downto 0)
);
end sig_read;
architecture sig_read of sig_read is
signal rst : std_logic;
signal h_cnt : unsigned(11 downto 0);
signal v_cnt : unsigned(11 downto 0);
signal one_screen : std_logic;
signal h_state : unsigned(1 downto 0);
signal h_state_m : unsigned(1 downto 0);
signal h_state_v : unsigned(1 downto 0);
signal h_state_i : unsigned(1 downto 0);
signal v_state : unsigned(1 downto 0);
signal v_state_m : unsigned(1 downto 0);
signal v_state_v : unsigned(1 downto 0);
signal v_state_i : unsigned(1 downto 0);
constant SYNC_OFF : unsigned(1 downto 0) := "00";
constant SYNC : unsigned(1 downto 0) := "01";
constant SYNC_BACK : unsigned(1 downto 0) := "10";
constant ACTIVE_LINE : unsigned(1 downto 0) := "11";
constant H_SYNC_BACK : unsigned(11 downto 0) := H_BLANKING - H_SYNC_OFFSET - H_SYNC_WIDTH;
constant V_SYNC_BACK : unsigned(11 downto 0) := V_BLANKING - V_SYNC_OFFSET - V_SYNC_WIDTH;
signal disp_rd_en : std_logic;
signal disp_rd_data : color_t(COLOR_CNT-1 downto 0);
signal px_fifo_rd_en : std_logic;
signal px_fifo_full : std_logic;
signal px_fifo_empty : std_logic;
signal px_fifo_cnt : std_logic_vector(10 downto 0);
signal px_fifo_dat_out : std_logic_vector(31 downto 0);
-- memory
signal mem_address : unsigned(27 downto 0);
signal mem_burst_len : unsigned( 5 downto 0);
signal mem_cmd_en : std_logic;
signal mem_rd_en : std_logic;
signal mem_rd_data : std_logic_vector(31 downto 0);
signal mem_rd_cnt : unsigned( 6 downto 0);
signal mem_fetch_cnt : unsigned( 5 downto 0);
signal mem_read_cnt : unsigned( 6 downto 0);
signal mem_read_wait : std_logic;
signal new_line : std_logic;
signal new_line_q0 : std_logic;
signal new_line_q1 : std_logic;
signal new_line_q2 : std_logic;
signal new_line_q3 : std_logic;
signal new_line_s : std_logic;
begin
rst <= not rst_n;
-- -------------------------------------------------------------------------------
-- MEMORY
-- -------------------------------------------------------------------------------
ddr2_cmd_byte_addr_o <= std_logic_vector(mem_address(27 downto 0) & "00");
ddr2_cmd_bl_o <= std_logic_vector(mem_burst_len);
ddr2_cmd_instr_o <= "001"; -- only read from this interface
ddr2_cmd_en_o <= mem_cmd_en;
ddr2_rd_en_o <= mem_rd_en;
mem_rd_cnt <= unsigned(ddr2_rd_count_i);
new_line <= '1' when h_state_v = SYNC and v_state_v = ACTIVE_LINE else '0';
new_line_s <= new_line and new_line_q0 and not new_line_q1 and not new_line_q2;
process (ddr2_clk, rst_n)
begin
if rst_n = '0' then
mem_address <= (others => '0');
mem_cmd_en <= '0';
mem_burst_len <= (others => '0');
mem_fetch_cnt <= (others => '0');
h_state_m <= (others => '0');
h_state_v <= (others => '0');
v_state_m <= (others => '0');
v_state_v <= (others => '0');
new_line_q0 <= '0';
new_line_q1 <= '0';
new_line_q2 <= '0';
new_line_q3 <= '0';
mem_read_cnt <= (others => '0');
mem_read_wait <= '0';
elsif rising_edge(ddr2_clk) then
new_line_q0 <= new_line;
new_line_q1 <= new_line_q0;
new_line_q2 <= new_line_q1;
new_line_q3 <= new_line_q2;
-- synchronizer
h_state_m <= h_state;
h_state_v <= h_state_m;
v_state_m <= v_state;
v_state_v <= v_state_m;
-- calculate memory fetch count
if new_line_s = '1' then
mem_fetch_cnt <= H_ACTIVE_PIXEL(11 downto 6);
elsif mem_cmd_en = '1' then
mem_fetch_cnt <= mem_fetch_cnt - "1";
end if;
-- wait state
if mem_cmd_en = '1' then
mem_read_wait <= '1';
elsif mem_read_cnt = "0101111" and mem_read_wait = '1' then
mem_read_wait <= '0';
end if;
-- mem raw read count
if mem_read_cnt = x"40" and mem_rd_en = '1' then
mem_read_cnt <= "0000001";
elsif mem_read_cnt = x"40" then
mem_read_cnt <= (others => '0');
elsif mem_rd_en = '1' then
mem_read_cnt <= mem_read_cnt + "1";
end if;
mem_cmd_en <= '0';
if ddr2_cmd_full_i = '0' and mem_fetch_cnt /= "000000" and mem_cmd_en = '0' and mem_read_wait = '0' then
mem_cmd_en <= '1';
mem_burst_len <= "111111";
end if;
if v_state_v = SYNC then
mem_address <= MEM_START_ADR(29 downto 2);
elsif mem_cmd_en = '1' then
mem_address <= mem_address + x"040";
end if;
end if;
end process;
mem_rd_data <= ddr2_rd_data_i;
mem_rd_en <= not ddr2_rd_empty_i;
px_fifo_0: entity work.px_fifo
port map (
wr_clk => ddr2_clk,
rd_clk => clk,
rst => rst,
din => mem_rd_data,
wr_en => mem_rd_en,
rd_en => px_fifo_rd_en,
dout => px_fifo_dat_out,
full => px_fifo_full,
empty => px_fifo_empty,
rd_data_count => px_fifo_cnt
);
px_fifo_rd_en <= disp_rd_en and not px_fifo_empty;
disp_rd_en <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
disp_rd_data <= (px_fifo_dat_out(23 downto 16), px_fifo_dat_out(15 downto 8), px_fifo_dat_out(7 downto 0))
when px_fifo_empty = '0' else
(x"ff", x"00", x"00");
-- -------------------------------------------------------------------------------
-- DISPLAY
-- -------------------------------------------------------------------------------
hsync_o <= '1' when h_state = SYNC and v_state = ACTIVE_LINE else '0';
vsync_o <= '1' when v_state = SYNC else '0';
color_en_o <= disp_rd_en;
color_o <= disp_rd_data;
--color_en_o <= '1' when h_state = ACTIVE_LINE and v_state = ACTIVE_LINE else '0';
--color_o <= ((others => v_cnt(3)), (others => v_cnt(2)), (others => v_cnt(1)));
process (clk, rst_n)
begin
if rst_n = '0' then
h_cnt <= x"000";
v_cnt <= x"000";
v_state <= "00";
v_state_i <= "00";
h_state <= "00";
h_state_i <= "00";
one_screen <= '0';
elsif rising_edge(clk) then
if v_state = ACTIVE_LINE and v_cnt = x"000" then
one_screen <= '0';
elsif en_stb_i = '1' then
one_screen <= '1';
end if;
if one_screen = '1' and h_cnt = x"000" then
h_state <= h_state_i;
case h_state_i is
when SYNC_OFF => h_cnt <= H_SYNC_OFFSET-1;
when SYNC => h_cnt <= H_SYNC_WIDTH-1;
when SYNC_BACK => h_cnt <= H_SYNC_BACK-1;
when ACTIVE_LINE => h_cnt <= H_ACTIVE_PIXEL-1;
when others => h_cnt <= x"000";
end case;
elsif h_cnt /= x"000" then
h_cnt <= h_cnt - "1";
end if;
if one_screen = '1' and h_cnt = x"000" then
h_state_i <= h_state_i + "01";
end if;
if one_screen = '1' and v_cnt = x"000" and h_state = SYNC_OFF then
v_state <= v_state_i;
case v_state_i is
when SYNC_OFF => v_cnt <= x"0" & V_SYNC_OFFSET;
when SYNC => v_cnt <= x"0" & V_SYNC_WIDTH;
when SYNC_BACK => v_cnt <= V_SYNC_BACK;
when ACTIVE_LINE => v_cnt <= V_ACTIVE_LINES;
when others => v_cnt <= x"000";
end case;
elsif v_cnt /= x"000" and (h_state = ACTIVE_LINE and h_cnt = x"000") then
v_cnt <= v_cnt - "1";
end if;
if one_screen = '1' and v_cnt = x"000" then
v_state_i <= v_state_i + "01";
end if;
end if;
end process;
end sig_read;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
ENTITY sig_read_tb IS
END sig_read_tb;
ARCHITECTURE rtl OF sig_read_tb IS
constant CLK_PERIOD : time := 10 ns;
constant CLK_PERIOD2: time := 5 ns;
signal clk : std_logic;
signal ddr2_clk : std_logic;
signal rst : std_logic;
signal rst_n : std_logic;
signal en_stb_i : std_logic;
signal hsync_o : std_logic;
signal vsync_o : std_logic;
signal color_en_o : std_logic;
signal color_o : color_t(COLOR_CNT-1 downto 0);
signal ddr2_rd_cmd_en_o : std_logic;
signal ddr2_rd_cmd_instr_o : std_logic_vector( 2 downto 0);
signal ddr2_rd_cmd_bl_o : std_logic_vector( 5 downto 0);
signal ddr2_rd_cmd_byte_addr_o : std_logic_vector(29 downto 0);
signal ddr2_rd_cmd_empty_i : std_logic;
signal ddr2_rd_cmd_full_i : std_logic;
signal ddr2_rd_en_o : std_logic;
signal ddr2_rd_data_i : std_logic_vector(31 downto 0);
signal ddr2_rd_full_i : std_logic;
signal ddr2_rd_empty_i : std_logic;
signal ddr2_rd_count_i : std_logic_vector( 6 downto 0);
signal ddr2_rd_overflow_i : std_logic;
signal ddr2_rd_error_i : std_logic;
signal ddr2_wr_cmd_en_o : std_logic;
signal ddr2_wr_cmd_instr_o : std_logic_vector( 2 downto 0);
signal ddr2_wr_cmd_bl_o : std_logic_vector( 5 downto 0);
signal ddr2_wr_cmd_byte_addr_o : std_logic_vector(29 downto 0);
signal ddr2_wr_cmd_empty_i : std_logic;
signal ddr2_wr_cmd_full_i : std_logic;
signal ddr2_wr_en_o : std_logic;
signal ddr2_wr_mask_o : std_logic_vector( 3 downto 0);
signal ddr2_wr_data_o : std_logic_vector(31 downto 0);
signal ddr2_wr_full_i : std_logic;
signal ddr2_wr_empty_i : std_logic;
signal ddr2_wr_count_i : std_logic_vector( 6 downto 0);
signal ddr2_wr_underrun_i : std_logic;
signal ddr2_wr_error_i : std_logic;
signal wr_cnt : unsigned( 7 downto 0);
signal wr_lat : unsigned( 7 downto 0);
signal en_stb_iq : std_logic;
signal hsync_oq : std_logic;
signal vsync_oq : std_logic;
signal color_en_oq : std_logic;
signal color_oq : color_t(COLOR_CNT-1 downto 0);
signal req_cnt : unsigned(15 downto 0);
signal req_save_cnt : unsigned(15 downto 0);
signal lat_cnt : unsigned(15 downto 0);
signal latency_done : std_logic;
signal latency : std_logic;
BEGIN
rst <= transport '1', '0' after ( 4 * CLK_PERIOD);
rst_n <= not rst;
clock: process
begin
clk <= '1', '0' after CLK_PERIOD/2;
wait for CLK_PERIOD;
end process;
ddr_clk: process
begin
ddr2_clk <= '1', '0' after CLK_PERIOD2/2;
wait for CLK_PERIOD2;
end process;
reg: process begin
wait until rising_edge(clk);
en_stb_iq <= en_stb_i;
hsync_o <= hsync_oq;
vsync_o <= vsync_oq;
color_o <= color_oq;
color_en_o <= color_en_oq;
end process;
dut_writ: entity work.sig_write
port map (
clk => clk,
rst_n => rst_n,
ctrl_disable_wr => '0',
ddr2_clk => ddr2_clk,
ddr2_cmd_en_o => ddr2_wr_cmd_en_o,
ddr2_cmd_instr_o => ddr2_wr_cmd_instr_o,
ddr2_cmd_bl_o => ddr2_wr_cmd_bl_o,
ddr2_cmd_byte_addr_o => ddr2_wr_cmd_byte_addr_o,
ddr2_cmd_empty_i => ddr2_wr_cmd_empty_i,
ddr2_cmd_full_i => ddr2_wr_cmd_full_i,
ddr2_wr_en_o => ddr2_wr_en_o,
ddr2_wr_mask_o => ddr2_wr_mask_o,
ddr2_wr_data_o => ddr2_wr_data_o,
ddr2_wr_full_i => ddr2_wr_full_i,
ddr2_wr_empty_i => ddr2_wr_empty_i,
ddr2_wr_count_i => ddr2_wr_count_i,
ddr2_wr_underrun_i => ddr2_wr_underrun_i,
ddr2_wr_error_i => ddr2_wr_error_i,
hsync_i => hsync_o,
vsync_i => vsync_o,
color_en_i => color_en_o,
color_i => color_o
);
mem_wr: process begin
ddr2_wr_cmd_empty_i <= '1';
ddr2_wr_underrun_i <= '0';
ddr2_wr_error_i <= '0';
wait;
end process;
ddr2_wr_empty_i <= '1' when wr_cnt = 0 else '0';
ddr2_wr_full_i <= wr_cnt(7);
ddr2_wr_count_i <= std_logic_vector(wr_cnt(6 downto 0));
ddr2_wr_cmd_full_i <= '1' when wr_lat /= x"00" else '0';
mem_wr_l: process (ddr2_clk, rst_n)
begin
if rst_n = '0' then
wr_cnt <= (others => '0');
wr_lat <= (others => '0');
elsif rising_edge(ddr2_clk) then
if wr_lat <= x"10" and wr_lat > x"00" and ddr2_wr_en_o = '1' then
wr_cnt <= wr_cnt - x"03";
elsif wr_lat <= x"10" and wr_lat > x"00" then
wr_cnt <= wr_cnt - x"04";
elsif ddr2_wr_en_o = '1' then
wr_cnt <= wr_cnt + "1";
end if;
if ddr2_wr_cmd_en_o = '1' then
wr_lat <= x"11";
end if;
if wr_lat /= x"00" then
wr_lat <= wr_lat - "1";
end if;
end if;
end process;
dut_read: entity work.sig_read
generic map (
H_ACTIVE_PIXEL => x"500",
H_BLANKING => x"198",
H_SYNC_WIDTH => x"070",
H_SYNC_OFFSET => x"030",
V_ACTIVE_LINES => x"400",
V_BLANKING => x"02a",
V_SYNC_WIDTH => x"01",
V_SYNC_OFFSET => x"03"
)
port map (
clk => clk,
rst_n => rst_n,
ddr2_clk => ddr2_clk,
ddr2_cmd_en_o => ddr2_rd_cmd_en_o,
ddr2_cmd_instr_o => ddr2_rd_cmd_instr_o,
ddr2_cmd_bl_o => ddr2_rd_cmd_bl_o,
ddr2_cmd_byte_addr_o => ddr2_rd_cmd_byte_addr_o,
ddr2_cmd_empty_i => ddr2_rd_cmd_empty_i,
ddr2_cmd_full_i => ddr2_rd_cmd_full_i,
ddr2_rd_en_o => ddr2_rd_en_o,
ddr2_rd_data_i => ddr2_rd_data_i,
ddr2_rd_full_i => ddr2_rd_full_i,
ddr2_rd_empty_i => ddr2_rd_empty_i,
ddr2_rd_count_i => ddr2_rd_count_i,
ddr2_rd_overflow_i => ddr2_rd_overflow_i,
ddr2_rd_error_i => ddr2_rd_error_i,
en_stb_i => en_stb_iq,
hsync_o => hsync_oq,
vsync_o => vsync_oq,
color_en_o => color_en_oq,
color_o => color_oq
);
beh: process begin
en_stb_i <= '0';
wait for 20*CLK_PERIOD;
en_stb_i <= '1';
--wait for CLK_PERIOD;
--en_stb_i <= '0';
wait;
end process;
mem_rd: process begin
ddr2_rd_cmd_empty_i <= '1';
ddr2_rd_data_i <= (others => '0');
ddr2_rd_overflow_i <= '0';
ddr2_rd_error_i <= '0';
wait;
end process;
ddr2_rd_count_i <= std_logic_vector(req_cnt(6 downto 0));
ddr2_rd_empty_i <= '0' when req_cnt /= x"0000" else '1';
ddr2_rd_cmd_full_i <= '1' when req_save_cnt /= x"0000" else '0';
ddr2_rd_full_i <= '1' when req_cnt = x"0040" else '0';
latency_done <= '1' when lat_cnt = x"0001" else '0';
mem_rd_l: process (ddr2_clk, rst_n)
begin
if rst_n = '0' then
req_cnt <= (others => '0');
req_save_cnt <= (others => '0');
lat_cnt <= (others => '0');
latency <= '1';
elsif rising_edge(ddr2_clk) then
if ddr2_rd_cmd_en_o = '1' then
req_save_cnt <= x"00" & "00" & unsigned(ddr2_rd_cmd_bl_o) + "1";
lat_cnt <= x"0020";
elsif latency_done = '1' then
req_save_cnt <= (others => '0');
end if;
if lat_cnt /= x"0000" then
lat_cnt <= lat_cnt - "1";
end if;
if latency_done = '1' and ddr2_rd_en_o = '1' then
req_cnt <= req_cnt + req_save_cnt - "1";
elsif latency_done = '1' then
req_cnt <= req_cnt + req_save_cnt;
elsif ddr2_rd_en_o = '1' and req_cnt /= x"0000" then
req_cnt <= req_cnt - "1";
end if;
end if;
end process;
end rtl;
configuration sig_read_tb_rtl_cfg of sig_read_tb is
for rtl
end for;
end sig_read_tb_rtl_cfg;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
ENTITY sig_tb IS
END sig_tb;
ARCHITECTURE rtl OF sig_tb IS
constant CLK_PERIOD : time := 20 ns;
signal clk : std_logic;
signal rst : std_logic;
signal rst_n : std_logic;
signal en_stb_i : std_logic;
signal hsync_o : std_logic;
signal vsync_o : std_logic;
signal color_en_o : std_logic;
signal color_o : color_t(COLOR_CNT-1 downto 0);
signal en_stb_iq : std_logic;
signal hsync_oq : std_logic;
signal vsync_oq : std_logic;
signal color_en_oq : std_logic;
signal color_oq : color_t(COLOR_CNT-1 downto 0);
BEGIN
rst <= transport '1', '0' after ( 4 * CLK_PERIOD);
rst_n <= not rst;
clock: process
begin
clk <= '1', '0' after CLK_PERIOD/2;
wait for CLK_PERIOD;
end process;
reg: process begin
wait until rising_edge(clk);
en_stb_iq <= en_stb_i;
hsync_o <= hsync_oq;
vsync_o <= vsync_oq;
color_o <= color_oq;
color_en_o <= color_en_oq;
end process;
dut: entity work.sig
generic map (
H_ACTIVE_PIXEL => x"500",
H_BLANKING => x"198",
H_SYNC_WIDTH => x"070",
H_SYNC_OFFSET => x"030",
V_ACTIVE_LINES => x"400",
V_BLANKING => x"02a",
V_SYNC_WIDTH => x"01",
V_SYNC_OFFSET => x"03"
)
port map (
clk => clk,
rst_n => rst_n,
en_stb_i => en_stb_iq,
hsync_o => hsync_oq,
vsync_o => vsync_oq,
color_en_o => color_en_oq,
color_o => color_oq
);
dut2: entity work.vga
port map (
pixelClock => clk,
Red => open,
Green => open,
Blue => open,
hSync => open,
vSync => open,
blank => open
);
beh: process begin
en_stb_i <= '0';
wait for 20*CLK_PERIOD;
en_stb_i <= '1';
--wait for CLK_PERIOD;
--en_stb_i <= '0';
wait;
end process;
end rtl;
configuration sig_tb_rtl_cfg of sig_tb is
for rtl
end for;
end sig_tb_rtl_cfg;

171
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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
entity sig_write is
generic (
MEM_START_ADR : unsigned(29 downto 0) := "00" & x"0000000"
);
port (
clk : in std_logic;
rst_n : in std_logic;
ctrl_disable_wr : in std_logic;
-- memory interface
ddr2_clk : in std_logic;
ddr2_cmd_en_o : out std_logic;
ddr2_cmd_instr_o : out std_logic_vector( 2 downto 0);
ddr2_cmd_bl_o : out std_logic_vector( 5 downto 0);
ddr2_cmd_byte_addr_o : out std_logic_vector(29 downto 0);
ddr2_cmd_empty_i : in std_logic;
ddr2_cmd_full_i : in std_logic;
ddr2_wr_en_o : out std_logic;
ddr2_wr_mask_o : out std_logic_vector( 3 downto 0);
ddr2_wr_data_o : out std_logic_vector(31 downto 0);
ddr2_wr_full_i : in std_logic;
ddr2_wr_empty_i : in std_logic;
ddr2_wr_count_i : in std_logic_vector( 6 downto 0);
ddr2_wr_underrun_i : in std_logic;
ddr2_wr_error_i : in std_logic;
-- display output
hsync_i : in std_logic;
vsync_i : in std_logic;
color_en_i : in std_logic;
color_i : in color_t(COLOR_CNT-1 downto 0)
);
end sig_write;
architecture sig_write of sig_write is
signal color_en_l : std_logic;
signal color_en_iq : std_logic;
signal rst : std_logic;
signal px_fifo_wr : std_logic;
signal px_fifo_full : std_logic;
signal px_fifo_empty : std_logic;
signal px_fifo_cnt : std_logic_vector(10 downto 0);
signal px_fifo_din : std_logic_vector(31 downto 0);
signal enabled : std_logic;
signal vsync : std_logic;
signal vsync_m : std_logic;
signal vsync_v : std_logic;
signal vsync_vq : std_logic;
signal vsync_sh : std_logic_vector( 3 downto 0);
-- memory
signal mem_address : unsigned(27 downto 0);
signal mem_cmd_en : std_logic;
signal mem_wr_en : std_logic;
signal mem_wr_data : std_logic_vector(31 downto 0);
signal px_cnt : unsigned( 7 downto 0);
begin
rst <= not rst_n;
-- -------------------------------------------------------------------------------
-- MEMORY
-- -------------------------------------------------------------------------------
ddr2_cmd_byte_addr_o <= std_logic_vector(mem_address(27 downto 0) & "00");
ddr2_cmd_bl_o <= "111111";
ddr2_cmd_instr_o <= "000";
ddr2_cmd_en_o <= mem_cmd_en;
ddr2_wr_data_o <= mem_wr_data;
ddr2_wr_en_o <= mem_wr_en;
ddr2_wr_mask_o <= (others => '0');
process (clk, rst_n)
begin
if rst_n = '0' then
enabled <= '0';
vsync <= '0';
elsif rising_edge(clk) then
-- eliminate glitches
vsync_sh <= vsync_sh(2 downto 0) & vsync_i;
if vsync_sh = "1111" then
vsync <= '1';
elsif vsync_sh = "0000" then
vsync <= '0';
end if;
-- freeze frame switch
if vsync = '1' then
if ctrl_disable_wr = '1' then
enabled <= '0';
else
enabled <= '1';
end if;
end if;
end if;
end process;
px_fifo_wr <= color_en_i and enabled;
px_fifo_din <= (31 downto 24 => '0') & color_i(RED) & color_i(GREEN) & color_i(BLUE);
px_fifo_0: entity work.px_fifo
port map (
wr_clk => clk,
rd_clk => ddr2_clk,
rst => rst,
din => px_fifo_din,
wr_en => px_fifo_wr,
rd_en => mem_wr_en,
dout => mem_wr_data,
full => px_fifo_full,
empty => px_fifo_empty,
rd_data_count => px_fifo_cnt
);
mem_wr_en <= '1' when px_fifo_empty = '0' and ddr2_wr_full_i = '0' else '0';
mem_cmd_en <= '1' when px_cnt = x"40" else '0';
process (ddr2_clk, rst_n)
begin
if rst_n = '0' then
px_cnt <= (others => '0');
mem_address <= (others => '0');
vsync_m <= '0';
vsync_v <= '0';
vsync_vq <= '0';
elsif rising_edge(ddr2_clk) then
-- signal synchronizer
vsync_m <= vsync;
vsync_v <= vsync_m;
vsync_vq <= vsync_v;
if mem_cmd_en = '1' and mem_wr_en = '1' then
px_cnt <= x"01";
elsif mem_cmd_en = '1' then
px_cnt <= (others => '0');
elsif mem_wr_en = '1' then
px_cnt <= px_cnt + "1";
end if;
if vsync_vq = '1' and vsync_v = '0' then
mem_address <= MEM_START_ADR(29 downto 2);
elsif mem_cmd_en = '1' then
mem_address <= mem_address + x"040";
end if;
end if;
end process;
end sig_write;

1
fpga/src/snippets Submodule

Submodule fpga/src/snippets added at 8893270fc3

93
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#FPGA_PART=xc6slx45-3-csg324
CONFIG VCCAUX = 3.3;
##############################################################################
# SYSCLK Input
##############################################################################
NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;
# Constraint for RX0
NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
##############################################################################
# Mechanical Switches (SW)
##############################################################################
#NET "switch<0>" LOC = "A10" |IOSTANDARD = LVCMOS33 ;
#NET "switch<1>" LOC = "D14" |IOSTANDARD = LVCMOS33 ;
#NET "switch<2>" LOC = "C14" | IOSTANDARD = LVCMOS33 ;
#NET "switch<3>" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
#############################################
## TMDS pairs for Atlys top OUT: J2 - Bank 0
#############################################
NET "tx0_tmds(3)" LOC = "B6" |IOSTANDARD = TMDS_33 ; # Clock
NET "tx0_tmds_n(3)" LOC = "A6" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(2)" LOC = "B8" |IOSTANDARD = TMDS_33 ; # Red
NET "tx0_tmds_n(2)" LOC = "A8" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(1)" LOC = "C7" |IOSTANDARD = TMDS_33 ; # Green
NET "tx0_tmds_n(1)" LOC = "A7" |IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(0)" LOC = "D8" |IOSTANDARD = TMDS_33 ; # Blue
NET "tx0_tmds_n(0)" LOC = "C8" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys top OUT: JA - Bank 2
## Use TML_33 to add output series termination
###############################################
#NET "tx1_tmds(3)" LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(2)" LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(1)" LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(0)" LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
#
###################################################
## TMDS pairs for Atlys IN (FPGA Bank 1): J3
###################################################
#NET "rx1_tmds(3)" LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(2)" LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(1)" LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(0)" LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys IN (FPGA Bank 0): J1
###############################################
NET "rx0_tmds(3)" LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(2)" LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(1)" LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(0)" LOC = "G9" |IOSTANDARD = TMDS_33 ; # Blue
NET "rx0_tmds_n(0)" LOC = "F9" |IOSTANDARD = TMDS_33 ;
NET "rx0_scl" LOC = "C13" |IOSTANDARD = LVCMOS33 ;
NET "rx0_sda" LOC = "A13" |IOSTANDARD = LVCMOS33 ;
########################################
# Reset button and LEDs and Mechanical Switches (SW)
########################################
NET "rstbtn_n" LOC = "T15" |IOSTANDARD = LVCMOS33;
NET "led<0>" LOC = "U18" |IOSTANDARD = LVCMOS33;
NET "led<1>" LOC = "M14" |IOSTANDARD = LVCMOS33;
NET "led<2>" LOC = "N14" |IOSTANDARD = LVCMOS33;
NET "led<3>" LOC = "L14" |IOSTANDARD = LVCMOS33;
NET "led<4>" LOC = "M13" |IOSTANDARD = LVCMOS33;
NET "led<5>" LOC = "D4" |IOSTANDARD = LVCMOS33;
NET "led<6>" LOC = "P16" |IOSTANDARD = LVCMOS33;
NET "led<7>" LOC = "N12" |IOSTANDARD = LVCMOS33;
# Multi-cycle paths for TX0 / encoder_0
#TIMEGRP "bramgrp_0" = RAMS(dvi_encoder_0/pixel2x/data_i<*>);
#TIMEGRP "fddbgrp_0" = FFS(dvi_encoder_0/pixel2x/db<*>);
#TIMEGRP "bramra_0" = FFS(dvi_encoder_0/pixel2x/ra<*>);
#
#TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
#TIMESPEC "TS_ramra_0" = FROM "bramra_0" TO "fddbgrp_0" TS_DVI_CLOCK0;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
library work;
use work.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity atlys is
generic ( MODE : string := "encode");
--generic ( MODE : string := "direct");
port (
rstbtn_n : in std_logic; -- The pink reset button
clk100 : in std_logic; -- 100 MHz osicallator
tx0_tmds : out std_logic_vector(3 downto 0);
tx0_tmds_n : out std_logic_vector(3 downto 0);
rx0_tmds : in std_logic_vector(3 downto 0);
rx0_tmds_n : in std_logic_vector(3 downto 0);
rx0_sda : inout std_logic;
rx0_scl : in std_logic;
tx1_tmds : out std_logic_vector(3 downto 0);
tx1_tmds_n : out std_logic_vector(3 downto 0);
rx1_tmds : in std_logic_vector(3 downto 0);
rx1_tmds_n : in std_logic_vector(3 downto 0);
switch : in std_logic_vector(1 downto 0);
led : out std_logic_vector(7 downto 0)
);
end atlys;
architecture top of atlys is
signal rstbtn : std_logic;
signal rst_n : std_logic;
signal rst : std_logic;
signal pclk : std_logic;
signal pclkx2 : std_logic;
signal pclkx10 : std_logic;
signal pllclk1 : std_logic;
signal pllclk1bg : std_logic;
signal pll_lckd : std_logic;
signal serdesstrobe : std_logic;
signal tmdsclk : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal dat_en : std_logic;
signal valid : std_logic_vector(COLOR_CNT-1 downto 0);
signal ready : std_logic_vector(COLOR_CNT-1 downto 0);
signal psalgnerr : std_logic;
signal color : color_t(COLOR_CNT-1 downto 0);
signal sdout : sdat_t(COLOR_CNT-1 downto 0);
signal rx0_sda_i : std_logic;
signal rx0_sda_o : std_logic;
signal rx0_tmds_s : std_logic_vector(3 downto 0);
signal toggle : std_logic;
signal tmdsclkint : std_logic_vector(4 downto 0);
type tmds_data_t is array(natural range <>) of std_logic_vector(4 downto 0);
signal tmds_data : tmds_data_t(COLOR_CNT-1 downto 0);
signal tmdsint : std_logic_vector(2 downto 0);
signal tmds_clk : std_logic;
signal sdata : std_logic_vector(29 downto 0);
signal tx0_pclkx2 : std_logic;
signal tx0_pclkx10 : std_logic;
signal tx0_reset_n : std_logic;
signal tx0_serdesstrobe : std_logic;
signal tx0_clkfbout : std_logic;
signal tx0_clkfbin : std_logic;
signal tx0_plllckd : std_logic;
signal tx0_pllclk0 : std_logic;
signal tx0_pllclk2 : std_logic;
signal tx0_bufpll_lock : std_logic;
begin
rstbtn <= not rstbtn_n;
rst <= not rst_n;
led <= ready(RED) & ready(GREEN) & ready(BLUE) & valid(RED) & valid(GREEN) & valid(BLUE) & dat_en & rst_n;
dvi_decoder_0: entity work.dvi_decoder
port map (
ext_rst => rstbtn,
tmdsclk_p => rx0_tmds(3),
tmdsclk_n => rx0_tmds_n(3),
din_p => rx0_tmds(2 downto 0),
din_n => rx0_tmds_n(2 downto 0),
reset_n => rst_n, -- rx reset
pclk_o => pclk, -- regenerated pixel clock
pclkx2_o => pclkx2, -- double rate pixel clock
pclkx10_o => pclkx10, -- 10x pixel as IOCLK
pll_lckd_o => pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL
serdesstrobe_o => serdesstrobe, -- BUFPLL serdesstrobe output
tmdsclk_o => tmdsclk, -- TMDS cable clock
hsync_o => hsync, -- hsync data
vsync_o => vsync, -- vsync data
dat_en_o => dat_en, -- data enable
valid_o => valid,
ready_o => ready,
psalgnerr_o => psalgnerr,
sdout_o => sdout,
color_o => color
);
direct: if MODE = "direct" generate
-- ----------------------------------------------------------
-- Forward TMDS Clock Using OSERDES2 block
-- ----------------------------------------------------------
process (pclkx2, rst_n)
begin
if rst_n = '0' then
toggle <= '0';
tmdsclkint <= (others => '0');
elsif rising_edge(pclkx2) then
toggle <= not toggle;
if toggle = '1' then
tmdsclkint <= (others => '1');
else
tmdsclkint <= (others => '0');
end if;
end if;
end process;
clkout: entity work.serdes_n_to_1
generic map (SF => 5)
port map (
ioclk => pclkx10,
gclk => pclkx2,
rst => rst,
serdesstrobe_i => serdesstrobe,
data_i => tmdsclkint,
data_o => tmds_clk
);
TMDS3: OBUFDS port map (I => tmds_clk, O => tx0_tmds(3), OB => tx0_tmds_n(3)); -- clock
d: for I in 0 to COLOR_CNT-1 generate
outI: entity work.serdes_n_to_1
generic map (SF => 5)
port map (
ioclk => pclkx10,
gclk => pclkx2,
rst => rst,
serdesstrobe_i => serdesstrobe,
data_i => tmds_data(I),
data_o => tmdsint(I)
);
tx_tmdsI: OBUFDS port map (i => tmdsint(I), o => tx0_tmds(I), ob => tx0_tmds_n(I));
end generate;
sdata <= sdout(RED)(9 downto 5) & sdout(GREEN)(9 downto 5) & sdout(BLUE)(9 downto 5)
& sdout(RED)(4 downto 0) & sdout(GREEN)(4 downto 0) & sdout(BLUE)(4 downto 0);
pixel2x: entity work.convert_30to15_fifo
port map (
rst => rst,
clk => pclk,
clkx2 => pclkx2,
data_i => sdata,
data_o( 4 downto 0) => tmds_data(0),
data_o( 9 downto 5) => tmds_data(1),
data_o(14 downto 10) => tmds_data(2)
);
end generate;
decode: if MODE = "encode" generate
-- ----------------------------------------------------------------------------
-- Instantiate a dedicate PLL for output port
-- ----------------------------------------------------------------------------
pll_oserdes_0: PLL_BASE
generic map (
CLKIN_PERIOD => 10.0,
CLKFBOUT_MULT => 10, --set VCO to 10x of CLKIN
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 10,
CLKOUT2_DIVIDE => 5,
COMPENSATION => "SOURCE_SYNCHRONOUS"
)
port map (
CLKFBOUT => tx0_clkfbout,
CLKOUT0 => tx0_pllclk0,
CLKOUT1 => open,
CLKOUT2 => tx0_pllclk2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => tx0_plllckd,
CLKFBIN => tx0_clkfbin,
CLKIN => pclk, -- pllclk1bg,
RST => rst
);
-- ----------------------------------------------------------------------------
-- This BUFG is needed in order to deskew between PLL clkin and clkout
-- So the tx0 pclkx2 and pclkx10 will have the same phase as the pclk input
-- ----------------------------------------------------------------------------
tx0_clkfb_buf: BUFG port map(I => tx0_clkfbout, O => tx0_clkfbin);
-- --------------------------------
-- regenerate pclkx2 for TX
-- --------------------------------
tx0_pclkx2_buf: BUFG port map(I => tx0_pllclk2, O => tx0_pclkx2);
-- --------------------------------
-- regenerate pclkx10 for TX
-- --------------------------------
tx0_ioclk_buf: BUFPLL
generic map ( DIVIDE => 5 )
port map (
PLLIN => tx0_pllclk0,
GCLK => tx0_pclkx2,
LOCKED => tx0_plllckd,
IOCLK => tx0_pclkx10,
SERDESSTROBE => tx0_serdesstrobe,
LOCK => tx0_bufpll_lock
);
tx0_reset_n <= tx0_bufpll_lock;
dvi_encoder_0: entity work.dvi_encoder
port map (
rst_n => tx0_reset_n,
pclk => pclk,
pclkx2 => tx0_pclkx2,
pclkx10 => tx0_pclkx10,
serdesstrobe_i => tx0_serdesstrobe,
color_i => color,
hsync_i => hsync,
vsync_i => vsync,
dat_en_i => dat_en,
tmds_p => tx0_tmds,
tmds_n => tx0_tmds_n
);
end generate;
-- ----------------------------------------------------------------------------
-- I2C EDID Emulation
-- ----------------------------------------------------------------------------
rx0_sda_i <= rx0_sda;
rx0_sda <= '0' when rx0_sda_o = '0' else 'Z';
i2c_rom_0: entity work.i2c_rom
port map (
clk => clk100,
rst_n => rstbtn_n,
sda_i => rx0_sda_i,
sda_o => rx0_sda_o,
scl_i => rx0_scl
);
end top;

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#FPGA_PART=xc6slx45-3-csg324
CONFIG VCCAUX = 3.3;
##############################################################################
# SYSCLK Input
##############################################################################
NET "clk100" LOC = "L15" | IOSTANDARD = LVCMOS33 | TNM_NET = clk100;
TIMESPEC TS_clk100 = PERIOD "clk100" 100 MHz HIGH 50%;
# Constraint for RX0
NET "dvi2ddr_0/dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
##############################################################################
# Mechanical Switches (SW)
##############################################################################
NET "switch<0>" LOC = "A10" |IOSTANDARD = LVCMOS33 ;
#NET "switch<1>" LOC = "D14" |IOSTANDARD = LVCMOS33 ;
#NET "switch<2>" LOC = "C14" | IOSTANDARD = LVCMOS33 ;
#NET "switch<3>" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
#############################################
## TMDS pairs for Atlys top OUT: J2 - Bank 0
#############################################
NET "tx0_tmds(3)" LOC = "B6" | IOSTANDARD = TMDS_33 ; # Clock
NET "tx0_tmds_n(3)" LOC = "A6" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(2)" LOC = "B8" | IOSTANDARD = TMDS_33 ; # Red
NET "tx0_tmds_n(2)" LOC = "A8" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(1)" LOC = "C7" | IOSTANDARD = TMDS_33 ; # Green
NET "tx0_tmds_n(1)" LOC = "A7" | IOSTANDARD = TMDS_33 ;
NET "tx0_tmds(0)" LOC = "D8" | IOSTANDARD = TMDS_33 ; # Blue
NET "tx0_tmds_n(0)" LOC = "C8" | IOSTANDARD = TMDS_33 ;
###############################################
## TMDS pairs for Atlys top OUT: JA - Bank 2
## Use TML_33 to add output series termination
###############################################
#NET "tx1_tmds(3)" LOC = "T9" |IOSTANDARD = TML_33; #TMDS_33 ; ## Clock
#NET "tx1_tmds_n(3)" LOC = "V9" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(2)" LOC = "N5" |IOSTANDARD = TML_33; #TMDS_33 ; ## Red
#NET "tx1_tmds_n(2)" LOC = "P6" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(1)" LOC = "T4" |IOSTANDARD = TML_33; #TMDS_33 ; ## Green
#NET "tx1_tmds_n(1)" LOC = "V4" |IOSTANDARD = TML_33; #TMDS_33 ; #
#NET "tx1_tmds(0)" LOC = "R3" |IOSTANDARD = TML_33; #TMDS_33 ; ## Blue
#NET "tx1_tmds_n(0)" LOC = "T3" |IOSTANDARD = TML_33; #TMDS_33 ; #
#
###################################################
## TMDS pairs for Atlys IN (FPGA Bank 1): J3
###################################################
#NET "rx1_tmds(3)" LOC = "H17" |IOSTANDARD = TMDS_33 ; # CLK
#NET "rx1_tmds_n(3)" LOC = "H18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(2)" LOC = "J16" |IOSTANDARD = TMDS_33 ; # Red
#NET "rx1_tmds_n(2)" LOC = "J18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(1)" LOC = "L17" |IOSTANDARD = TMDS_33 ; # Green
#NET "rx1_tmds_n(1)" LOC = "L18" |IOSTANDARD = TMDS_33 ;
#NET "rx1_tmds(0)" LOC = "K17" |IOSTANDARD = TMDS_33 ; # Blue
#NET "rx1_tmds_n(0)" LOC = "K18" |IOSTANDARD = TMDS_33 ;
#
###############################################
## TMDS pairs for Atlys IN (FPGA Bank 0): J1
###############################################
NET "rx0_tmds(3)" LOC = "D11" |IOSTANDARD = TMDS_33 ; # CLK
NET "rx0_tmds_n(3)" LOC = "C11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(2)" LOC = "B12" |IOSTANDARD = TMDS_33 ; # Red
NET "rx0_tmds_n(2)" LOC = "A12" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(1)" LOC = "B11" |IOSTANDARD = TMDS_33 ; # Green
NET "rx0_tmds_n(1)" LOC = "A11" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(0)" LOC = "G9" |IOSTANDARD = TMDS_33 ; # Blue
NET "rx0_tmds_n(0)" LOC = "F9" |IOSTANDARD = TMDS_33 ;
NET "rx0_scl" LOC = "C13" |IOSTANDARD = LVCMOS33 ;
NET "rx0_sda" LOC = "A13" |IOSTANDARD = LVCMOS33 ;
########################################
# Reset button and LEDs and Mechanical Switches (SW)
########################################
NET "rstbtn_n" LOC = "T15" | IOSTANDARD = LVCMOS33;
NET "led<0>" LOC = "U18" | IOSTANDARD = LVCMOS33;
NET "led<1>" LOC = "M14" | IOSTANDARD = LVCMOS33;
NET "led<2>" LOC = "N14" | IOSTANDARD = LVCMOS33;
NET "led<3>" LOC = "L14" | IOSTANDARD = LVCMOS33;
NET "led<4>" LOC = "M13" | IOSTANDARD = LVCMOS33;
NET "led<5>" LOC = "D4" | IOSTANDARD = LVCMOS33;
NET "led<6>" LOC = "P16" | IOSTANDARD = LVCMOS33;
NET "led<7>" LOC = "N12" | IOSTANDARD = LVCMOS33;
# Multi-cycle paths for TX0 / encoder_0
TIMEGRP "bramgrp_0" = RAMS(ddr2dvi_0/dvi_encoder_0/pixel2x/data_int<*>);
TIMEGRP "fddbgrp_0" = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/db<*>);
TIMEGRP "bramra_0" = FFS(ddr2dvi_0/dvi_encoder_0/pixel2x/ra<*>);
TIMESPEC "TS_ramdo_0" = FROM "bramgrp_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
TIMESPEC "TS_ramra_0" = FROM "bramra_0" TO "fddbgrp_0" TS_DVI_CLOCK0;
#######################################################################################
#### onBoard USB controller
#######################################################################################
####NET "UsbMode" LOC = "A5"; # Bank = 0, Pin name = IO_L6N, Sch name = U1-INT0#
NET "usb_clk" LOC = "C10" | IOSTANDARD = LVCMOS33 | TNM_NET = clk48; # Bank = 0, Pin name = IO_L37P_GCLK13, Sch name = U1-IFCLK
TIMESPEC TS_clk48 = PERIOD "clk48" 48 MHz HIGH 50%;
NET "usb_flag_a" LOC = "B9" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
NET "usb_flag_b" LOC = "A9" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB
NET "usb_flag_c" LOC = "C15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC
NET "usb_cs" LOC = "B2" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2P, Sch name = U1-SLCS
NET "usb_oe" LOC = "A15" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L64N_SCP4, Sch name = U1-SLOE
NET "usb_rd" LOC = "F13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD
NET "usb_wr" LOC = "E13" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L63N_SCP6, Sch name = U1-SLWR
NET "usb_pktend" LOC = "C4" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L1N_VREF, Sch name = U1-PKTEND
NET "usb_adr<0>" LOC = "A14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62N_VREF, Sch name = U1-FIFOAD0
NET "usb_adr<1>" LOC = "B14" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L62P, Sch name = U1-FIFOAD1
NET "usb_dat<0>" LOC = "A2" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0
NET "usb_dat<1>" LOC = "D6" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1
NET "usb_dat<2>" LOC = "C6" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2
NET "usb_dat<3>" LOC = "B3" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3
NET "usb_dat<4>" LOC = "A3" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4
NET "usb_dat<5>" LOC = "B4" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5
NET "usb_dat<6>" LOC = "A4" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6
NET "usb_dat<7>" LOC = "C5" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7
#######################################################################################
#### SIG READ
#######################################################################################
# FIXME: for now just TIG between the FIFO clocks
TIMESPEC "TS_async_0" = FROM "ddr2dvi_0_pclk_buf" TO "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TIG;
TIMESPEC "TS_async_1" = FROM "ddr2_0_memc3_infrastructure_inst_clk0_bufg_in" TO "ddr2dvi_0_pclk_buf" TIG;
#######################################################################################
#### DDR2
#######################################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#NET "c?_pll_lock" TIG;
#INST "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "ddr2_0/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
NET "ddr2_dq[*]" IN_TERM = NONE;
NET "ddr2_dqs" IN_TERM = NONE;
NET "ddr2_dqs_n" IN_TERM = NONE;
NET "ddr2_udqs" IN_TERM = NONE;
NET "ddr2_udqs_n" IN_TERM = NONE;
NET "ddr2_clk" LOC = "G3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
NET "ddr2_clk_n" LOC = "G1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
NET "ddr2_cke" LOC = "H7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
NET "ddr2_ras_n" LOC = "L5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
NET "ddr2_cas_n" LOC = "K5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
NET "ddr2_we_n" LOC = "E3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
NET "ddr2_rzq" LOC = "L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = RZQ
NET "ddr2_zio" LOC = "C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = ZIO
NET "ddr2_ba<0>" LOC = "F2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
NET "ddr2_ba<1>" LOC = "F1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
NET "ddr2_ba<2>" LOC = "E1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2
NET "ddr2_a<0>" LOC = "J7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
NET "ddr2_a<1>" LOC = "J6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
NET "ddr2_a<2>" LOC = "H5" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
NET "ddr2_a<3>" LOC = "L7" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
NET "ddr2_a<4>" LOC = "F3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
NET "ddr2_a<5>" LOC = "H4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
NET "ddr2_a<6>" LOC = "H3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
NET "ddr2_a<7>" LOC = "H6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
NET "ddr2_a<8>" LOC = "D2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
NET "ddr2_a<9>" LOC = "D1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
NET "ddr2_a<10>" LOC = "F4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
NET "ddr2_a<11>" LOC = "D3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
NET "ddr2_a<12>" LOC = "G6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12
NET "ddr2_dq<0>" LOC = "L2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
NET "ddr2_dq<1>" LOC = "L1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
NET "ddr2_dq<2>" LOC = "K2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
NET "ddr2_dq<3>" LOC = "K1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
NET "ddr2_dq<4>" LOC = "H2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
NET "ddr2_dq<5>" LOC = "H1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
NET "ddr2_dq<6>" LOC = "J3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
NET "ddr2_dq<7>" LOC = "J1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
NET "ddr2_dq<8>" LOC = "M3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
NET "ddr2_dq<9>" LOC = "M1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
NET "ddr2_dq<10>" LOC = "N2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
NET "ddr2_dq<11>" LOC = "N1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
NET "ddr2_dq<12>" LOC = "T2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
NET "ddr2_dq<13>" LOC = "T1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
NET "ddr2_dq<14>" LOC = "U2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
NET "ddr2_dq<15>" LOC = "U1" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15
NET "ddr2_udqs" LOC="P2" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
NET "ddr2_udqs_n" LOC="P1" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
NET "ddr2_dqs" LOC="L4" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
NET "ddr2_dqs_n" LOC="L3" | IOSTANDARD = DIFF_SSTL18_I; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
NET "ddr2_dm" LOC="K3" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
NET "ddr2_udm" LOC="K4" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = DDR-UDM
NET "ddr2_odt" LOC="K6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT
NET "ddr2_zio" LOC="C2" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L83P, Sch name = DDR-ODT
# NET "ddr2_rzm" LOC="L6" | IOSTANDARD = SSTL18_I; # Bank = 3, Pin name = IO_L31P, Sch name = DDR-ODT

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dvi_package.all;
use work.strm_package.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity atlys_sig is
port (
rstbtn_n : in std_logic; -- The pink reset button
clk100 : in std_logic; -- 100 MHz osicallator
-- HDMI
tx0_tmds : out std_logic_vector(3 downto 0);
tx0_tmds_n : out std_logic_vector(3 downto 0);
rx0_tmds : in std_logic_vector(3 downto 0);
rx0_tmds_n : in std_logic_vector(3 downto 0);
rx0_sda : inout std_logic;
rx0_scl : in std_logic;
-- DDR2
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector( 2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_odt : out std_logic;
ddr2_cke : out std_logic;
ddr2_dm : out std_logic;
ddr2_udqs : inout std_logic;
ddr2_udqs_n : inout std_logic;
ddr2_rzq : inout std_logic;
ddr2_zio : inout std_logic;
ddr2_udm : out std_logic;
ddr2_dqs : inout std_logic;
ddr2_dqs_n : inout std_logic;
ddr2_clk : out std_logic;
ddr2_clk_n : out std_logic;
-- cypress interface
usb_clk : in std_logic;
usb_flag_a : in std_logic; -- programmable flag
usb_flag_b : in std_logic; -- full flag
usb_flag_c : in std_logic; -- empty flag
usb_cs : inout std_logic; -- put to GND, not need for this application
usb_oe : out std_logic; -- active_low
usb_rd : out std_logic; -- active_low
usb_wr : out std_logic; -- active_low
usb_pktend : out std_logic; -- active_low
usb_adr : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
usb_dat : inout std_logic_vector(7 downto 0);
switch : in std_logic_vector(0 downto 0);
led : out std_logic_vector(7 downto 0)
);
end atlys_sig;
architecture top of atlys_sig is
signal rstbtn : std_logic;
signal rst_n : std_logic;
signal rst : std_logic;
signal rst_pll : std_logic;
-- hdmi rx0
signal rx0_sda_i : std_logic;
signal rx0_sda_o : std_logic;
signal rx0_ddr2_cmd_en : std_logic;
signal rx0_ddr2_cmd_instr : std_logic_vector( 2 downto 0);
signal rx0_ddr2_cmd_bl : std_logic_vector( 5 downto 0);
signal rx0_ddr2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal rx0_ddr2_cmd_empty : std_logic;
signal rx0_ddr2_cmd_full : std_logic;
signal rx0_ddr2_wr_en : std_logic;
signal rx0_ddr2_wr_mask : std_logic_vector( 3 downto 0);
signal rx0_ddr2_wr_data : std_logic_vector(31 downto 0);
signal rx0_ddr2_wr_full : std_logic;
signal rx0_ddr2_wr_empty : std_logic;
signal rx0_ddr2_wr_count : std_logic_vector( 6 downto 0);
signal rx0_ddr2_wr_underrun : std_logic;
signal rx0_ddr2_wr_error : std_logic;
-- hdmi tx0
signal tx0_pll_locked : std_logic;
signal tx0_ddr2_cmd_en : std_logic;
signal tx0_ddr2_cmd_instr : std_logic_vector( 2 downto 0);
signal tx0_ddr2_cmd_bl : std_logic_vector( 5 downto 0);
signal tx0_ddr2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal tx0_ddr2_cmd_empty : std_logic;
signal tx0_ddr2_cmd_full : std_logic;
signal tx0_ddr2_rd_en : std_logic;
signal tx0_ddr2_rd_data : std_logic_vector(31 downto 0);
signal tx0_ddr2_rd_full : std_logic;
signal tx0_ddr2_rd_empty : std_logic;
signal tx0_ddr2_rd_count : std_logic_vector( 6 downto 0);
signal tx0_ddr2_rd_overflow : std_logic;
signal tx0_ddr2_rd_error : std_logic;
-- ddr2
signal clk333 : std_logic;
signal clk333in : std_logic;
signal ddr2_calib_done : std_logic;
signal ddr2_clk_out : std_logic;
signal ddr2_rst_out : std_logic;
-- strm cy_usb
constant STRM_DDR2_BUS : integer := 0;
constant STRM_OUT_SLV_CNT : integer := 1;
signal strm_in_data : std_logic_vector(31 downto 0);
signal strm_in_eop : std_logic;
signal strm_in_sop : std_logic;
signal strm_in_en : std_logic;
signal strm_in_busy : std_logic;
signal strm_out_slv_reqs : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_slv_busy : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_data : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_eop : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_en : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
-- strm ddr2
signal strm_ddr2_cmd_en : std_logic;
signal strm_ddr2_cmd_instr : std_logic_vector( 2 downto 0);
signal strm_ddr2_cmd_bl : std_logic_vector( 5 downto 0);
signal strm_ddr2_cmd_byte_addr : std_logic_vector(29 downto 0);
signal strm_ddr2_cmd_empty : std_logic;
signal strm_ddr2_cmd_full : std_logic;
signal strm_ddr2_wr_en : std_logic;
signal strm_ddr2_wr_mask : std_logic_vector( 3 downto 0);
signal strm_ddr2_wr_data : std_logic_vector(31 downto 0);
signal strm_ddr2_wr_full : std_logic;
signal strm_ddr2_wr_empty : std_logic;
signal strm_ddr2_wr_count : std_logic_vector( 6 downto 0);
signal strm_ddr2_wr_underrun : std_logic;
signal strm_ddr2_wr_error : std_logic;
signal strm_ddr2_rd_en : std_logic;
signal strm_ddr2_rd_data : std_logic_vector(31 downto 0);
signal strm_ddr2_rd_full : std_logic;
signal strm_ddr2_rd_empty : std_logic;
signal strm_ddr2_rd_count : std_logic_vector( 6 downto 0);
signal strm_ddr2_rd_overflow : std_logic;
signal strm_ddr2_rd_error : std_logic;
signal ddr2_strm_in_busy : std_logic;
signal ddr2_strm_out_req : std_logic;
signal ddr2_strm_out_busy : std_logic;
signal ddr2_strm_out_data : std_logic_vector(31 downto 0);
signal ddr2_strm_out_eop : std_logic;
signal ddr2_strm_out_en : std_logic;
signal debug_usb : std_logic_vector( 7 downto 0);
signal debug_strm_ddr2 : std_logic_vector( 7 downto 0);
begin
rstbtn <= not rstbtn_n;
rst_pll <= ddr2_rst_out;
rst_n <= not ddr2_rst_out and tx0_pll_locked;
rst <= not rst_n;
led <= (others => '0');
dvi2ddr_0: entity work.dvi2ddr
port map (
clk => ddr2_clk_out,
rst => ddr2_rst_out,
ctrl_disable_wr => switch(0),
rx_tmds => rx0_tmds,
rx_tmds_n => rx0_tmds_n,
-- memory interface
ddr2_cmd_en_o => rx0_ddr2_cmd_en,
ddr2_cmd_instr_o => rx0_ddr2_cmd_instr,
ddr2_cmd_bl_o => rx0_ddr2_cmd_bl,
ddr2_cmd_byte_addr_o => rx0_ddr2_cmd_byte_addr,
ddr2_cmd_empty_i => rx0_ddr2_cmd_empty,
ddr2_cmd_full_i => rx0_ddr2_cmd_full,
ddr2_wr_en_o => rx0_ddr2_wr_en,
ddr2_wr_mask_o => rx0_ddr2_wr_mask,
ddr2_wr_data_o => rx0_ddr2_wr_data,
ddr2_wr_full_i => rx0_ddr2_wr_full,
ddr2_wr_empty_i => rx0_ddr2_wr_empty,
ddr2_wr_count_i => rx0_ddr2_wr_count,
ddr2_wr_underrun_i => rx0_ddr2_wr_underrun,
ddr2_wr_error_i => rx0_ddr2_wr_error
);
-- ----------------------------------------------------------------------------
-- I2C EDID Emulation
-- ----------------------------------------------------------------------------
rx0_sda_i <= rx0_sda;
rx0_sda <= '0' when rx0_sda_o = '0' else 'Z';
i2c_rom_0: entity work.i2c_rom
port map (
clk => ddr2_clk_out,
rst_n => rst_n,
sda_i => rx0_sda_i,
sda_o => rx0_sda_o,
scl_i => rx0_scl
);
-- ----------------------------------------------------------------------------
-- DDR2
-- ----------------------------------------------------------------------------
ddr2_0: entity work.ddr2
port map (
c3_sys_clk => clk100,
c3_sys_rst_i => rstbtn,
c3_calib_done => ddr2_calib_done,
c3_clk0 => ddr2_clk_out,
c3_rst0 => ddr2_rst_out,
mcb3_dram_dq => ddr2_dq,
mcb3_dram_a => ddr2_a,
mcb3_dram_ba => ddr2_ba,
mcb3_dram_ras_n => ddr2_ras_n,
mcb3_dram_cas_n => ddr2_cas_n,
mcb3_dram_we_n => ddr2_we_n,
mcb3_dram_odt => ddr2_odt,
mcb3_dram_cke => ddr2_cke,
mcb3_dram_dm => ddr2_dm,
mcb3_dram_udqs => ddr2_udqs,
mcb3_dram_udqs_n => ddr2_udqs_n,
mcb3_rzq => ddr2_rzq,
mcb3_zio => ddr2_zio,
mcb3_dram_udm => ddr2_udm,
mcb3_dram_dqs => ddr2_dqs,
mcb3_dram_dqs_n => ddr2_dqs_n,
mcb3_dram_ck => ddr2_clk,
mcb3_dram_ck_n => ddr2_clk_n,
c3_p0_cmd_clk => ddr2_clk_out,
c3_p0_cmd_en => tx0_ddr2_cmd_en,
c3_p0_cmd_instr => tx0_ddr2_cmd_instr,
c3_p0_cmd_bl => tx0_ddr2_cmd_bl,
c3_p0_cmd_byte_addr => tx0_ddr2_cmd_byte_addr,
c3_p0_cmd_empty => tx0_ddr2_cmd_empty,
c3_p0_cmd_full => tx0_ddr2_cmd_full,
c3_p0_wr_clk => ddr2_clk_out,
c3_p0_wr_en => '0',
c3_p0_wr_mask => (others => '0'),
c3_p0_wr_data => (others => '0'),
c3_p0_wr_full => open,
c3_p0_wr_empty => open,
c3_p0_wr_count => open,
c3_p0_wr_underrun => open,
c3_p0_wr_error => open,
c3_p0_rd_clk => ddr2_clk_out,
c3_p0_rd_en => tx0_ddr2_rd_en,
c3_p0_rd_data => tx0_ddr2_rd_data,
c3_p0_rd_full => tx0_ddr2_rd_full,
c3_p0_rd_empty => tx0_ddr2_rd_empty,
c3_p0_rd_count => tx0_ddr2_rd_count,
c3_p0_rd_overflow => tx0_ddr2_rd_overflow,
c3_p0_rd_error => tx0_ddr2_rd_error,
c3_p1_cmd_clk => ddr2_clk_out,
c3_p1_cmd_en => rx0_ddr2_cmd_en,
c3_p1_cmd_instr => rx0_ddr2_cmd_instr,
c3_p1_cmd_bl => rx0_ddr2_cmd_bl,
c3_p1_cmd_byte_addr => rx0_ddr2_cmd_byte_addr,
c3_p1_cmd_empty => rx0_ddr2_cmd_empty,
c3_p1_cmd_full => rx0_ddr2_cmd_full,
c3_p1_wr_clk => ddr2_clk_out,
c3_p1_wr_en => rx0_ddr2_wr_en,
c3_p1_wr_mask => rx0_ddr2_wr_mask,
c3_p1_wr_data => rx0_ddr2_wr_data,
c3_p1_wr_full => rx0_ddr2_wr_full,
c3_p1_wr_empty => rx0_ddr2_wr_empty,
c3_p1_wr_count => rx0_ddr2_wr_count,
c3_p1_wr_underrun => rx0_ddr2_wr_underrun,
c3_p1_wr_error => rx0_ddr2_wr_error,
c3_p1_rd_clk => ddr2_clk_out,
c3_p1_rd_en => '0',
c3_p1_rd_data => open,
c3_p1_rd_full => open,
c3_p1_rd_empty => open,
c3_p1_rd_count => open,
c3_p1_rd_overflow => open,
c3_p1_rd_error => open,
c3_p2_cmd_clk => ddr2_clk_out,
c3_p2_cmd_en => strm_ddr2_cmd_en,
c3_p2_cmd_instr => strm_ddr2_cmd_instr,
c3_p2_cmd_bl => strm_ddr2_cmd_bl,
c3_p2_cmd_byte_addr => strm_ddr2_cmd_byte_addr,
c3_p2_cmd_empty => strm_ddr2_cmd_empty,
c3_p2_cmd_full => strm_ddr2_cmd_full,
c3_p2_wr_clk => ddr2_clk_out,
c3_p2_wr_en => strm_ddr2_wr_en,
c3_p2_wr_mask => strm_ddr2_wr_mask,
c3_p2_wr_data => strm_ddr2_wr_data,
c3_p2_wr_full => strm_ddr2_wr_full,
c3_p2_wr_empty => strm_ddr2_wr_empty,
c3_p2_wr_count => strm_ddr2_wr_count,
c3_p2_wr_underrun => strm_ddr2_wr_underrun,
c3_p2_wr_error => strm_ddr2_wr_error,
c3_p2_rd_clk => ddr2_clk_out,
c3_p2_rd_en => strm_ddr2_rd_en,
c3_p2_rd_data => strm_ddr2_rd_data,
c3_p2_rd_full => strm_ddr2_rd_full,
c3_p2_rd_empty => strm_ddr2_rd_empty,
c3_p2_rd_count => strm_ddr2_rd_count,
c3_p2_rd_overflow => strm_ddr2_rd_overflow,
c3_p2_rd_error => strm_ddr2_rd_error,
c3_p3_cmd_clk => '0',
c3_p3_cmd_en => '0',
c3_p3_cmd_instr => (others => '0'),
c3_p3_cmd_bl => (others => '0'),
c3_p3_cmd_byte_addr => (others => '0'),
c3_p3_cmd_empty => open,
c3_p3_cmd_full => open,
c3_p3_wr_clk => '0',
c3_p3_wr_en => '0',
c3_p3_wr_mask => (others => '0'),
c3_p3_wr_data => (others => '0'),
c3_p3_wr_full => open,
c3_p3_wr_empty => open,
c3_p3_wr_count => open,
c3_p3_wr_underrun => open,
c3_p3_wr_error => open,
c3_p3_rd_clk => '0',
c3_p3_rd_en => '0',
c3_p3_rd_data => open,
c3_p3_rd_full => open,
c3_p3_rd_empty => open,
c3_p3_rd_count => open,
c3_p3_rd_overflow => open,
c3_p3_rd_error => open
);
ddr2dvi_0: entity work.ddr2dvi
port map (
clk => ddr2_clk_out,
rst_n => rst_n,
rst_pll => rst_pll,
tx_tmds => tx0_tmds,
tx_tmds_n => tx0_tmds_n,
tx_pll_locked_o => tx0_pll_locked,
-- memory interface
ddr2_cmd_en_o => tx0_ddr2_cmd_en,
ddr2_cmd_instr_o => tx0_ddr2_cmd_instr,
ddr2_cmd_bl_o => tx0_ddr2_cmd_bl,
ddr2_cmd_byte_addr_o => tx0_ddr2_cmd_byte_addr,
ddr2_cmd_empty_i => tx0_ddr2_cmd_empty,
ddr2_cmd_full_i => tx0_ddr2_cmd_full,
ddr2_rd_en_o => tx0_ddr2_rd_en,
ddr2_rd_data_i => tx0_ddr2_rd_data,
ddr2_rd_full_i => tx0_ddr2_rd_full,
ddr2_rd_empty_i => tx0_ddr2_rd_empty,
ddr2_rd_count_i => tx0_ddr2_rd_count,
ddr2_rd_overflow_i => tx0_ddr2_rd_overflow,
ddr2_rd_error_i => tx0_ddr2_rd_error
);
-- ----------------------------------------------------------------------------
-- USB
-- ----------------------------------------------------------------------------
f2p_strm_top_0: entity work.f2p_strm_top
generic map (STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT)
port map (
clk => ddr2_clk_out,
rst_n => rst_n,
debug => debug_usb,
-- cypress interface
usb_clk => usb_clk,
usb_flag_a_i => usb_flag_a,
usb_flag_b_i => usb_flag_b,
usb_flag_c_i => usb_flag_c,
usb_cs_o => usb_cs,
usb_oe_o => usb_oe,
usb_rd_o => usb_rd,
usb_wr_o => usb_wr,
usb_pktend_o => usb_pktend,
usb_adr_o => usb_adr,
usb_dat_io => usb_dat,
-- streaming bus
strm_in_data_o => strm_in_data,
strm_in_eop_o => strm_in_eop,
strm_in_sop_o => strm_in_sop,
strm_in_en_o => strm_in_en,
strm_in_busy_i => strm_in_busy,
strm_out_slv_reqs_i => strm_out_slv_reqs,
strm_out_slv_busy_o => strm_out_slv_busy,
strm_out_data_i => strm_out_data,
strm_out_eop_i => strm_out_eop,
strm_out_en_i => strm_out_en
);
strm_out_slv_reqs(STRM_DDR2_BUS) <= ddr2_strm_out_req;
strm_out_eop(STRM_DDR2_BUS) <= ddr2_strm_out_eop;
strm_out_en(STRM_DDR2_BUS) <= ddr2_strm_out_en;
strm_out_data(STRM_DDR2_BUS) <= ddr2_strm_out_data;
ddr2_strm_out_busy <= strm_out_slv_busy(STRM_DDR2_BUS);
strm_in_busy <= ddr2_strm_in_busy;
strm_ddr2_0: entity work.strm_ddr2
port map (
clk => ddr2_clk_out,
rst_n => rst_n,
debug => debug_strm_ddr2,
-- streaming bus
strm_in_data_i => strm_in_data,
strm_in_eop_i => strm_in_eop,
strm_in_sop_i => strm_in_sop,
strm_in_en_i => strm_in_en,
strm_in_busy_o => ddr2_strm_in_busy,
strm_out_req_o => ddr2_strm_out_req,
strm_out_busy_i => ddr2_strm_out_busy,
strm_out_data_o => ddr2_strm_out_data,
strm_out_eop_o => ddr2_strm_out_eop,
strm_out_en_o => ddr2_strm_out_en,
-- memory interface
ddr2_cmd_en_o => strm_ddr2_cmd_en,
ddr2_cmd_instr_o => strm_ddr2_cmd_instr,
ddr2_cmd_bl_o => strm_ddr2_cmd_bl,
ddr2_cmd_byte_addr_o => strm_ddr2_cmd_byte_addr,
ddr2_cmd_empty_i => strm_ddr2_cmd_empty,
ddr2_cmd_full_i => strm_ddr2_cmd_full,
ddr2_wr_en_o => strm_ddr2_wr_en,
ddr2_wr_mask_o => strm_ddr2_wr_mask,
ddr2_wr_data_o => strm_ddr2_wr_data,
ddr2_wr_full_i => strm_ddr2_wr_full,
ddr2_wr_empty_i => strm_ddr2_wr_empty,
ddr2_wr_count_i => strm_ddr2_wr_count,
ddr2_wr_underrun_i => strm_ddr2_wr_underrun,
ddr2_wr_error_i => strm_ddr2_wr_error,
ddr2_rd_en_o => strm_ddr2_rd_en,
ddr2_rd_data_i => strm_ddr2_rd_data,
ddr2_rd_full_i => strm_ddr2_rd_full,
ddr2_rd_empty_i => strm_ddr2_rd_empty,
ddr2_rd_count_i => strm_ddr2_rd_count,
ddr2_rd_overflow_i => strm_ddr2_rd_overflow,
ddr2_rd_error_i => strm_ddr2_rd_error
);
end top;

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#FPGA_PART=xc6slx9-2tqg144
CONFIG VCCAUX = 3.3;
###############################################################################
## SYSCLK/RESET Input
###############################################################################
NET "clk100_i" LOC = "P84" | IOSTANDARD = LVCMOS33 | TNM_NET = "clk100_i";
TIMESPEC TS_clk100_i = PERIOD "clk100_i" 100 MHz HIGH 50%;
NET "usb_clk_i" TNM_NET = "usb_clk_i";
TIMESPEC "TS_usb_clk_i" = PERIOD "usb_clk_i" 20.833 ns HIGH 50% INPUT_JITTER 208.33ps;
## Constraint for RX0
NET "dvi_decoder_0/rxclk" TNM_NET = DVI_CLOCK0;
TIMESPEC TS_DVI_CLOCK0 = PERIOD "DVI_CLOCK0" 100 MHz HIGH 50%;
## allow
#PIN "dvi_decoder_0/pclkbufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
################################################
### TMDS pairs
################################################
NET "rx0_tmds(3)" LOC = "P132" |IOSTANDARD = TMDS_33 ; # CLK
NET "rx0_tmds_n(3)" LOC = "P131" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(2)" LOC = "P134" |IOSTANDARD = TMDS_33 ; # Red
NET "rx0_tmds_n(2)" LOC = "P133" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(1)" LOC = "P140" |IOSTANDARD = TMDS_33 ; # Green
NET "rx0_tmds_n(1)" LOC = "P139" |IOSTANDARD = TMDS_33 ;
NET "rx0_tmds(0)" LOC = "P144" |IOSTANDARD = TMDS_33 ; # Blue
NET "rx0_tmds_n(0)" LOC = "P143" |IOSTANDARD = TMDS_33 ;
##NET "rx0_scl" LOC = "C13" |IOSTANDARD = LVCMOS33 ;
##NET "rx0_sda" LOC = "A13" |IOSTANDARD = LVCMOS33 ;
#######################################################################################
#### onBoard USB controller
#######################################################################################
NET "usb_clk_i" LOC = "P16" | IOSTANDARD = LVCMOS33;
NET "usb_flag_a_i" LOC = "P10" | IOSTANDARD = LVCMOS33;
NET "usb_flag_b_i" LOC = "P9" | IOSTANDARD = LVCMOS33;
NET "usb_flag_c_i" LOC = "P8" | IOSTANDARD = LVCMOS33;
NET "usb_cs_io" LOC = "P142" | IOSTANDARD = LVCMOS33;
NET "usb_oe_o" LOC = "P6" | IOSTANDARD = LVCMOS33;
NET "usb_rd_o" LOC = "P116" | IOSTANDARD = LVCMOS33;
NET "usb_wr_o" LOC = "P117" | IOSTANDARD = LVCMOS33;
NET "usb_pktend_o" LOC = "P1" | IOSTANDARD = LVCMOS33;
NET "usb_adr_o<0>" LOC = "P5" | IOSTANDARD = LVCMOS33;
NET "usb_adr_o<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<0>" LOC = "P23" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<1>" LOC = "P22" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<2>" LOC = "P21" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<3>" LOC = "P17" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<4>" LOC = "P15" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<5>" LOC = "P14" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<6>" LOC = "P12" | IOSTANDARD = LVCMOS33;
NET "usb_dat_io<7>" LOC = "P11" | IOSTANDARD = LVCMOS33;
#########################################
## VMC header
#########################################
NET "vmc_clk_o" LOC = "P55" | IOSTANDARD = LVCMOS33;
NET "vmc_hsync_o" LOC = "P61" | IOSTANDARD = LVCMOS33;
NET "vmc_vsync_o" LOC = "P62" | IOSTANDARD = LVCMOS33;
NET "vmc_de_o" LOC = "P66" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<0>" LOC = "P59" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<1>" LOC = "P51" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<2>" LOC = "P58" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<3>" LOC = "P50" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<4>" LOC = "P57" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<5>" LOC = "P48" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<6>" LOC = "P56" | IOSTANDARD = LVCMOS33;
NET "vmc_red_o<7>" LOC = "P47" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<0>" LOC = "P46" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<1>" LOC = "P41" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<2>" LOC = "P45" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<3>" LOC = "P40" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<4>" LOC = "P44" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<5>" LOC = "P39" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<6>" LOC = "P43" | IOSTANDARD = LVCMOS33;
NET "vmc_green_o<7>" LOC = "P38" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<0>" LOC = "P35" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<1>" LOC = "P30" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<2>" LOC = "P34" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<3>" LOC = "P29" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<4>" LOC = "P33" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<5>" LOC = "P27" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<6>" LOC = "P32" | IOSTANDARD = LVCMOS33;
NET "vmc_blue_o<7>" LOC = "P26" | IOSTANDARD = LVCMOS33;
#########################################
## Reset button and LEDs and Mechanical Switches (SW)
#########################################
#PIN "rstbtn_n" TIG;
#NET "rstbtn_n" LOC = "" |IOSTANDARD = LVCMOS33;
NET "led_o<0>" LOC = "P75" | IOSTANDARD = LVCMOS33;
NET "led_o<1>" LOC = "P78" | IOSTANDARD = LVCMOS33;
NET "led_o<2>" LOC = "P79" | IOSTANDARD = LVCMOS33;
NET "led_o<3>" LOC = "P80" | IOSTANDARD = LVCMOS33;

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-- -----------------------------------------------------------------------------
-- Copyright (c) 2013 Benjamin Krill <benjamin@krll.de>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.dvi_package.all;
use work.strm_package.all;
library work;
use work.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity dmb is
port (
clk100_i : in std_logic; -- 100 MHz osicallator
-- HDMI
rx0_tmds : in std_logic_vector(3 downto 0);
rx0_tmds_n : in std_logic_vector(3 downto 0);
--rx0_sda : inout std_logic;
--rx0_scl : in std_logic;
-- vcm
vmc_clk_o : out std_logic;
vmc_red_o : out std_logic_vector(7 downto 0);
vmc_green_o : out std_logic_vector(7 downto 0);
vmc_blue_o : out std_logic_vector(7 downto 0);
vmc_hsync_o : out std_logic;
vmc_vsync_o : out std_logic;
vmc_de_o : out std_logic;
-- cypress interface
usb_clk_i : in std_logic;
usb_flag_a_i : in std_logic; -- programmable flag
usb_flag_b_i : in std_logic; -- full flag
usb_flag_c_i : in std_logic; -- empty flag
usb_cs_io : inout std_logic; -- put to GND, not need for this application
usb_oe_o : out std_logic; -- active_low
usb_rd_o : out std_logic; -- active_low
usb_wr_o : out std_logic; -- active_low
usb_pktend_o : out std_logic; -- active_low
usb_adr_o : out std_logic_vector(1 downto 0); -- 00 ep2, 01 ep4, 10 ep6, 11 ep8
usb_dat_io : inout std_logic_vector(7 downto 0);
led_o : out std_logic_vector(3 downto 0)
);
end dmb;
architecture top of dmb is
signal rst_n : std_logic;
signal rstbtn : std_logic;
-- hdmi
signal pclk : std_logic;
signal pclkx2 : std_logic;
signal pclkx10 : std_logic;
signal pll_lckd : std_logic;
signal serdesstrobe : std_logic;
signal tmdsclk : std_logic;
signal hsync : std_logic;
signal vsync : std_logic;
signal dat_en : std_logic;
signal valid : std_logic_vector(COLOR_CNT-1 downto 0);
signal ready : std_logic_vector(COLOR_CNT-1 downto 0);
signal psalgnerr : std_logic;
signal color : color_t(COLOR_CNT-1 downto 0);
signal sdout : sdat_t(COLOR_CNT-1 downto 0);
-- clockinga
signal usb_rst_n : std_logic;
signal usb_clk_locked : std_logic;
signal usb_clk_gb : std_logic;
signal usb_clk_ib : std_logic;
signal usb_clk : std_logic;
signal rst100_n : std_logic;
signal clk100_locked : std_logic;
signal clk100_ib : std_logic;
signal clk100_gb : std_logic;
signal clk48_gb : std_logic;
signal clk100 : std_logic;
signal clk48 : std_logic;
-- strm cy_usb
constant STRM_REGFILE_BUS : integer := 0;
constant STRM_OUT_SLV_CNT : integer := 1;
signal strm_in_data : std_logic_vector(31 downto 0);
signal strm_in_eop : std_logic;
signal strm_in_sop : std_logic;
signal strm_in_en : std_logic;
signal strm_in_busy : std_logic;
signal strm_out_slv_reqs : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_slv_busy : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_data : strm_dat_bus_t(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_eop : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
signal strm_out_en : std_logic_vector(STRM_OUT_SLV_CNT-1 downto 0);
-- regfile
signal rf_strm_in_busy : std_logic;
signal rf_strm_out_req : std_logic;
signal rf_strm_out_busy : std_logic;
signal rf_strm_out_data : std_logic_vector(31 downto 0);
signal rf_strm_out_eop : std_logic;
signal rf_strm_out_en : std_logic;
constant REG_CNT : integer := 8;
signal regfile : std_logic_vector((32*REG_CNT)-1 downto 0);
signal test : std_logic;
begin
rstbtn <= '0';
usb_rst_n <= usb_clk_locked;
rst100_n <= clk100_locked;
led_o <= regfile(2 downto 0) & test;
-- ----------------------------------------------------------------------------
-- clocking
-- ----------------------------------------------------------------------------
-- USB
ibufg_usb_clk: IBUFG port map (O => usb_clk_ib, I => usb_clk_i);
bufg_usb_clk: BUFG port map (O => usb_clk, I => usb_clk_gb);
dcm_usb_clk: DCM_SP
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.833,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLKIN => usb_clk_ib,
CLKFB => usb_clk,
-- Output clocks
CLK0 => usb_clk_gb,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => usb_clk_locked,
STATUS => open,
RST => rstbtn,
-- Unused pin, tie low
DSSEN => '0'
);
-- MAIN
process (clk100, rst100_n)
begin
if rst100_n = '0' then
test <= '0';
elsif rising_edge(clk100) then
test <= not test;
end if;
end process;
ibufg_clk100: IBUFG port map (O => clk100_ib, I => clk100_i);
bufg_clk100: BUFG port map (O => clk100, I => clk100_gb);
bufg_clk48: BUFG port map (O => clk48, I => clk48_gb);
dcm_clk100: DCM_SP
generic map (
CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 12,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLKIN => clk100_ib,
CLKFB => clk100,
-- Output clocks
CLK0 => clk100_gb,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clk48_gb,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => clk100_locked,
STATUS => open,
RST => rstbtn,
-- Unused pin, tie low
DSSEN => '0'
);
dvi_decoder_0: entity work.dvi_decoder
port map (
ext_rst => rstbtn,
tmdsclk_p => rx0_tmds(3),
tmdsclk_n => rx0_tmds_n(3),
din_p => rx0_tmds(2 downto 0),
din_n => rx0_tmds_n(2 downto 0),
reset_n => rst_n, -- rx reset
pclk_o => pclk, -- regenerated pixel clock
pclkx2_o => pclkx2, -- double rate pixel clock
pclkx10_o => pclkx10, -- 10x pixel as IOCLK
pll_lckd_o => pll_lckd, -- send pll_lckd out so it can be fed into a different BUFPLL
serdesstrobe_o => serdesstrobe, -- BUFPLL serdesstrobe output
tmdsclk_o => tmdsclk, -- TMDS cable clock
hsync_o => hsync, -- hsync data
vsync_o => vsync, -- vsync data
dat_en_o => dat_en, -- data enable
valid_o => valid,
ready_o => ready,
psalgnerr_o => psalgnerr,
sdout_o => sdout,
color_o => color
);
vmc_clk_ddr: ODDR2
port map (
Q => vmc_clk_o, -- 1-bit DDR output data
C0 => pclk, -- clock input
C1 => not pclk, -- clock input, inverted
CE => '1', -- clock enable always
D0 => '1', -- sampled on clock posedge, output when clock is HIGH
D1 => '0', -- sampled on clock negedge, output when clock is LOW
R => '0', -- set/reset disabled
S => '1' -- set/reset disabled
);
--vmc_clk_o <= pclk;
vmc_red_o <= color(RED);
vmc_green_o <= color(GREEN);
vmc_blue_o <= color(BLUE);
vmc_hsync_o <= hsync;
vmc_vsync_o <= vsync;
vmc_de_o <= dat_en;
-- ----------------------------------------------------------------------------
-- core logic
-- ----------------------------------------------------------------------------
f2p_strm_top_0: entity work.f2p_strm_top
generic map (STRM_OUT_SLV_CNT => STRM_OUT_SLV_CNT)
port map (
clk => usb_clk,
rst_n => usb_rst_n,
debug => open,
-- cypress interface
usb_clk => usb_clk,
usb_flag_a_i => usb_flag_a_i,
usb_flag_b_i => usb_flag_b_i,
usb_flag_c_i => usb_flag_c_i,
usb_cs_o => usb_cs_io,
usb_oe_o => usb_oe_o,
usb_rd_o => usb_rd_o,
usb_wr_o => usb_wr_o,
usb_pktend_o => usb_pktend_o,
usb_adr_o => usb_adr_o,
usb_dat_io => usb_dat_io,
-- streaming bus
strm_in_data_o => strm_in_data,
strm_in_eop_o => strm_in_eop,
strm_in_sop_o => strm_in_sop,
strm_in_en_o => strm_in_en,
strm_in_busy_i => strm_in_busy,
strm_out_slv_reqs_i => strm_out_slv_reqs,
strm_out_slv_busy_o => strm_out_slv_busy,
strm_out_data_i => strm_out_data,
strm_out_eop_i => strm_out_eop,
strm_out_en_i => strm_out_en
);
strm_out_slv_reqs(STRM_REGFILE_BUS) <= rf_strm_out_req;
strm_out_eop(STRM_REGFILE_BUS) <= rf_strm_out_eop;
strm_out_en(STRM_REGFILE_BUS) <= rf_strm_out_en;
strm_out_data(STRM_REGFILE_BUS) <= rf_strm_out_data;
rf_strm_out_busy <= strm_out_slv_busy(STRM_REGFILE_BUS);
strm_in_busy <= rf_strm_in_busy;
strm_regfile_0: entity work.strm_regfile
generic map ( REGISTER_CNT => REG_CNT )
port map (
clk => usb_clk,
rst_n => usb_rst_n,
debug => open,
-- streaming bus
strm_in_data_i => strm_in_data,
strm_in_eop_i => strm_in_eop,
strm_in_sop_i => strm_in_sop,
strm_in_en_i => strm_in_en,
strm_in_busy_o => rf_strm_in_busy,
strm_out_req_o => rf_strm_out_req,
strm_out_busy_i => rf_strm_out_busy,
strm_out_data_o => rf_strm_out_data,
strm_out_eop_o => rf_strm_out_eop,
strm_out_en_o => rf_strm_out_en,
-- regfile
regfile_i => regfile,
regfile_o => regfile
);
end top;

9
fpga/src/vendor/xilinx/atlys_ddr2/coregen.cgp vendored Normal file
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true

37
fpga/src/vendor/xilinx/atlys_ddr2/create_ddr2.tcl vendored Normal file
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##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:mig:3.92" "ddr2" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-3csg324 VHDL ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result

49
fpga/src/vendor/xilinx/atlys_ddr2/ddr2.gise vendored Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ddr2.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1377105194" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377105194">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3822657174530342864" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="7467621048142235521" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1379695224" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8481875126579356750" xil_pn:start_ts="1379695224">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2.ncf vendored Normal file
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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Sun Jul 28 12:10:25 2013
## Generated by MIG Version 3.92
##
############################################################################
## File name : ddr2.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx45-csg324
## Speedgrade: -3
## Design Entry: VHDL
## Design: without Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
## Supported Part Numbers: MT47H64M16HR-25E
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "mcb3_dram_a[0]" LOC = "J7" ;
NET "mcb3_dram_a[10]" LOC = "F4" ;
NET "mcb3_dram_a[11]" LOC = "D3" ;
NET "mcb3_dram_a[12]" LOC = "G6" ;
NET "mcb3_dram_a[1]" LOC = "J6" ;
NET "mcb3_dram_a[2]" LOC = "H5" ;
NET "mcb3_dram_a[3]" LOC = "L7" ;
NET "mcb3_dram_a[4]" LOC = "F3" ;
NET "mcb3_dram_a[5]" LOC = "H4" ;
NET "mcb3_dram_a[6]" LOC = "H3" ;
NET "mcb3_dram_a[7]" LOC = "H6" ;
NET "mcb3_dram_a[8]" LOC = "D2" ;
NET "mcb3_dram_a[9]" LOC = "D1" ;
NET "mcb3_dram_ba[0]" LOC = "F2" ;
NET "mcb3_dram_ba[1]" LOC = "F1" ;
NET "mcb3_dram_ba[2]" LOC = "E1" ;
NET "mcb3_dram_cas_n" LOC = "K5" ;
NET "mcb3_dram_ck" LOC = "G3" ;
NET "mcb3_dram_ck_n" LOC = "G1" ;
NET "mcb3_dram_cke" LOC = "H7" ;
NET "mcb3_dram_dm" LOC = "K3" ;
NET "mcb3_dram_dq[0]" LOC = "L2" ;
NET "mcb3_dram_dq[10]" LOC = "N2" ;
NET "mcb3_dram_dq[11]" LOC = "N1" ;
NET "mcb3_dram_dq[12]" LOC = "T2" ;
NET "mcb3_dram_dq[13]" LOC = "T1" ;
NET "mcb3_dram_dq[14]" LOC = "U2" ;
NET "mcb3_dram_dq[15]" LOC = "U1" ;
NET "mcb3_dram_dq[1]" LOC = "L1" ;
NET "mcb3_dram_dq[2]" LOC = "K2" ;
NET "mcb3_dram_dq[3]" LOC = "K1" ;
NET "mcb3_dram_dq[4]" LOC = "H2" ;
NET "mcb3_dram_dq[5]" LOC = "H1" ;
NET "mcb3_dram_dq[6]" LOC = "J3" ;
NET "mcb3_dram_dq[7]" LOC = "J1" ;
NET "mcb3_dram_dq[8]" LOC = "M3" ;
NET "mcb3_dram_dq[9]" LOC = "M1" ;
NET "mcb3_dram_dqs" LOC = "L4" ;
NET "mcb3_dram_dqs_n" LOC = "L3" ;
NET "mcb3_dram_odt" LOC = "K6" ;
NET "mcb3_dram_ras_n" LOC = "L5" ;
NET "c3_sys_clk" LOC = "R10" ;
NET "c3_sys_rst_i" LOC = "M8" ;
NET "mcb3_dram_udm" LOC = "K4" ;
NET "mcb3_dram_udqs" LOC = "P2" ;
NET "mcb3_dram_udqs_n" LOC = "P1" ;
NET "mcb3_dram_we_n" LOC = "E3" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_rzq" LOC = "N4" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_zio" LOC = "P4" ;

365
fpga/src/vendor/xilinx/atlys_ddr2/ddr2.vho vendored Normal file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2.vho
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:19:03 $
-- \ \ / \ Date Created : Fri Aug 7 2009
-- \___\/\___\
--
-- Purpose : Template file containing code that can be used as a model
-- for instantiating a CORE Generator module in a HDL design.
-- Revision History:
--*****************************************************************************
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component ddr2
generic(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
C3_RST_ACT_LOW : integer := 0;
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
C3_CALIB_SOFT_IP : string := "TRUE";
C3_SIMULATION : string := "FALSE";
DEBUG_EN : integer := 0;
C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
C3_NUM_DQ_PINS : integer := 16;
C3_MEM_ADDR_WIDTH : integer := 13;
C3_MEM_BANKADDR_WIDTH : integer := 3
);
port (
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic
);
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
u_ddr2 : ddr2
generic map (
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C3_SIMULATION => C3_SIMULATION,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH
)
port map (
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p0_cmd_clk => c3_p0_cmd_clk,
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => c3_p0_wr_clk,
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => c3_p0_rd_clk,
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error,
c3_p1_cmd_clk => c3_p1_cmd_clk,
c3_p1_cmd_en => c3_p1_cmd_en,
c3_p1_cmd_instr => c3_p1_cmd_instr,
c3_p1_cmd_bl => c3_p1_cmd_bl,
c3_p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
c3_p1_cmd_empty => c3_p1_cmd_empty,
c3_p1_cmd_full => c3_p1_cmd_full,
c3_p1_wr_clk => c3_p1_wr_clk,
c3_p1_wr_en => c3_p1_wr_en,
c3_p1_wr_mask => c3_p1_wr_mask,
c3_p1_wr_data => c3_p1_wr_data,
c3_p1_wr_full => c3_p1_wr_full,
c3_p1_wr_empty => c3_p1_wr_empty,
c3_p1_wr_count => c3_p1_wr_count,
c3_p1_wr_underrun => c3_p1_wr_underrun,
c3_p1_wr_error => c3_p1_wr_error,
c3_p1_rd_clk => c3_p1_rd_clk,
c3_p1_rd_en => c3_p1_rd_en,
c3_p1_rd_data => c3_p1_rd_data,
c3_p1_rd_full => c3_p1_rd_full,
c3_p1_rd_empty => c3_p1_rd_empty,
c3_p1_rd_count => c3_p1_rd_count,
c3_p1_rd_overflow => c3_p1_rd_overflow,
c3_p1_rd_error => c3_p1_rd_error,
c3_p2_cmd_clk => c3_p2_cmd_clk,
c3_p2_cmd_en => c3_p2_cmd_en,
c3_p2_cmd_instr => c3_p2_cmd_instr,
c3_p2_cmd_bl => c3_p2_cmd_bl,
c3_p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
c3_p2_cmd_empty => c3_p2_cmd_empty,
c3_p2_cmd_full => c3_p2_cmd_full,
c3_p2_wr_clk => c3_p2_wr_clk,
c3_p2_wr_en => c3_p2_wr_en,
c3_p2_wr_mask => c3_p2_wr_mask,
c3_p2_wr_data => c3_p2_wr_data,
c3_p2_wr_full => c3_p2_wr_full,
c3_p2_wr_empty => c3_p2_wr_empty,
c3_p2_wr_count => c3_p2_wr_count,
c3_p2_wr_underrun => c3_p2_wr_underrun,
c3_p2_wr_error => c3_p2_wr_error,
c3_p2_rd_clk => c3_p2_rd_clk,
c3_p2_rd_en => c3_p2_rd_en,
c3_p2_rd_data => c3_p2_rd_data,
c3_p2_rd_full => c3_p2_rd_full,
c3_p2_rd_empty => c3_p2_rd_empty,
c3_p2_rd_count => c3_p2_rd_count,
c3_p2_rd_overflow => c3_p2_rd_overflow,
c3_p2_rd_error => c3_p2_rd_error,
c3_p3_cmd_clk => c3_p3_cmd_clk,
c3_p3_cmd_en => c3_p3_cmd_en,
c3_p3_cmd_instr => c3_p3_cmd_instr,
c3_p3_cmd_bl => c3_p3_cmd_bl,
c3_p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
c3_p3_cmd_empty => c3_p3_cmd_empty,
c3_p3_cmd_full => c3_p3_cmd_full,
c3_p3_wr_clk => c3_p3_wr_clk,
c3_p3_wr_en => c3_p3_wr_en,
c3_p3_wr_mask => c3_p3_wr_mask,
c3_p3_wr_data => c3_p3_wr_data,
c3_p3_wr_full => c3_p3_wr_full,
c3_p3_wr_empty => c3_p3_wr_empty,
c3_p3_wr_count => c3_p3_wr_count,
c3_p3_wr_underrun => c3_p3_wr_underrun,
c3_p3_wr_error => c3_p3_wr_error,
c3_p3_rd_clk => c3_p3_rd_clk,
c3_p3_rd_en => c3_p3_rd_en,
c3_p3_rd_data => c3_p3_rd_data,
c3_p3_rd_full => c3_p3_rd_full,
c3_p3_rd_empty => c3_p3_rd_empty,
c3_p3_rd_count => c3_p3_rd_count,
c3_p3_rd_overflow => c3_p3_rd_overflow,
c3_p3_rd_error => c3_p3_rd_error
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file ddr2.vhd when simulating
-- the core, ddr2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2.xco vendored Normal file
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##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Sun Jul 28 10:10:27 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:mig:3.92
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
# END Select
# BEGIN Parameters
CSET component_name=ddr2
CSET xml_input_file=./ddr2/user_design/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-06-08T23:00:50Z
# END Extra information
GENERATE
# CRC: ede738a9

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="ddr2/user_design/rtl/ddr2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="ddr2/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="ddr2/user_design/par/ddr2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ddr2|arc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="ddr2/user_design/rtl/ddr2.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ddr2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="ddr2" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-07-28T12:10:31" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1E4028521BF14C180A8024C9024AB5B9" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/ddr2" xil_pn:name="ddr2/user_design/par/ddr2.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/datasheet.txt vendored Normal file
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CORE Generator Options:
Target Device : xc6slx45-csg324
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : ddr2
No of Controllers : 1
Hardware Test Bench : enabled
/*******************************************************/
/* Controller 3 */
/*******************************************************/
Controller Options :
Memory : DDR2_SDRAM
Interface : NATIVE
Design Clock Frequency : 3000 ps (333.33 MHz)
Memory Type : Components
Memory Part : MT47H64M16XX-25E
Equivalent Part(s) : MT47H64M16HR-25E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 4(010)
CAS Latency : 5
DQS# Enable : Enable
DLL Enable : Enable-Normal
OCD Operation : OCD Exit
Output Drive Strength : Fullstrength
Outputs : Enable
Additive Latency (AL) : 0
RDQS Enable : Disable
RTT (nominal) - ODT : 50ohms
High Temparature Self Refresh Rate : Disable
User Interface Parameters :
Configuration Type : Four 32-bit bi-directional ports
Ports Selected : Port0, Port1, Port2, Port3
Memory Address Mapping : BANK_ROW_COLUMN
Arbitration Algorithm : Round Robin
Arbitration :
Time Slot0 : 0123
Time Slot1 : 1230
Time Slot2 : 2301
Time Slot3 : 3012
Time Slot4 : 0123
Time Slot5 : 1230
Time Slot6 : 2301
Time Slot7 : 3012
Time Slot8 : 0123
Time Slot9 : 1230
Time Slot10: 2301
Time Slot11: 3012
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : CALIB_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/create_ise.sh vendored Executable file
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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : create_ise.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
xtclsh set_ise_prop.tcl

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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Sun Jul 28 12:10:23 2013
## Generated by MIG Version 3.92
##
############################################################################
## File name : example_top.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx45-csg324
## Speedgrade: -3
## Design Entry: VHDL
## Design: with Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
## Supported Part Numbers: MT47H64M16HR-25E
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# Status Signals
############################################################################
NET "error" IOSTANDARD = LVCMOS18 ;
NET "calib_done" IOSTANDARD = LVCMOS18 ;
NET "calib_done" LOC = "B2" ;
NET "error" LOC = "A2" ;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "mcb3_dram_a[0]" LOC = "J7" ;
NET "mcb3_dram_a[10]" LOC = "F4" ;
NET "mcb3_dram_a[11]" LOC = "D3" ;
NET "mcb3_dram_a[12]" LOC = "G6" ;
NET "mcb3_dram_a[1]" LOC = "J6" ;
NET "mcb3_dram_a[2]" LOC = "H5" ;
NET "mcb3_dram_a[3]" LOC = "L7" ;
NET "mcb3_dram_a[4]" LOC = "F3" ;
NET "mcb3_dram_a[5]" LOC = "H4" ;
NET "mcb3_dram_a[6]" LOC = "H3" ;
NET "mcb3_dram_a[7]" LOC = "H6" ;
NET "mcb3_dram_a[8]" LOC = "D2" ;
NET "mcb3_dram_a[9]" LOC = "D1" ;
NET "mcb3_dram_ba[0]" LOC = "F2" ;
NET "mcb3_dram_ba[1]" LOC = "F1" ;
NET "mcb3_dram_ba[2]" LOC = "E1" ;
NET "mcb3_dram_cas_n" LOC = "K5" ;
NET "mcb3_dram_ck" LOC = "G3" ;
NET "mcb3_dram_ck_n" LOC = "G1" ;
NET "mcb3_dram_cke" LOC = "H7" ;
NET "mcb3_dram_dm" LOC = "K3" ;
NET "mcb3_dram_dq[0]" LOC = "L2" ;
NET "mcb3_dram_dq[10]" LOC = "N2" ;
NET "mcb3_dram_dq[11]" LOC = "N1" ;
NET "mcb3_dram_dq[12]" LOC = "T2" ;
NET "mcb3_dram_dq[13]" LOC = "T1" ;
NET "mcb3_dram_dq[14]" LOC = "U2" ;
NET "mcb3_dram_dq[15]" LOC = "U1" ;
NET "mcb3_dram_dq[1]" LOC = "L1" ;
NET "mcb3_dram_dq[2]" LOC = "K2" ;
NET "mcb3_dram_dq[3]" LOC = "K1" ;
NET "mcb3_dram_dq[4]" LOC = "H2" ;
NET "mcb3_dram_dq[5]" LOC = "H1" ;
NET "mcb3_dram_dq[6]" LOC = "J3" ;
NET "mcb3_dram_dq[7]" LOC = "J1" ;
NET "mcb3_dram_dq[8]" LOC = "M3" ;
NET "mcb3_dram_dq[9]" LOC = "M1" ;
NET "mcb3_dram_dqs" LOC = "L4" ;
NET "mcb3_dram_dqs_n" LOC = "L3" ;
NET "mcb3_dram_odt" LOC = "K6" ;
NET "mcb3_dram_ras_n" LOC = "L5" ;
NET "c3_sys_clk" LOC = "R10" ;
NET "c3_sys_rst_i" LOC = "M8" ;
NET "mcb3_dram_udm" LOC = "K4" ;
NET "mcb3_dram_udqs" LOC = "P2" ;
NET "mcb3_dram_udqs_n" LOC = "P1" ;
NET "mcb3_dram_we_n" LOC = "E3" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_rzq" LOC = "N4" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_zio" LOC = "P4" ;

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##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 07:09:11 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
# END Select
# BEGIN Parameters
CSET component_name=icon
CSET enable_jtag_bufg=true
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: 7da1f376

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##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 06:55:40 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET component_name=ila
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=2
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
GENERATE
# CRC: eff89f81

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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : ise_flow.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE batch mode
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
echo Synthesis Tool: XST
mkdir "../synth/__projnav" > ise_flow_results.txt
mkdir "../synth/xst" >> ise_flow_results.txt
mkdir "../synth/xst/work" >> ise_flow_results.txt
xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
ngdbuild -intstyle ise -dd ../synth/_ngo -uc example_top.ucf -p xc6slx45csg324-3 example_top.ngc example_top.ngd >> ise_flow_results.txt
map -intstyle ise -detail -w -pr off -c 100 -o example_top_map.ncd example_top.ngd example_top.pcf >> ise_flow_results.txt
par -w -intstyle ise -ol std example_top_map.ncd example_top.ncd example_top.pcf >> ise_flow_results.txt
trce -e 100 example_top.ncd example_top.pcf >> ise_flow_results.txt
bitgen -intstyle ise -f mem_interface_top.ut example_top.ncd >> ise_flow_results.txt
echo done!

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set -tmpdir ../synth/__projnav
set -xsthdpdir ../synth/xst
run
#Source Parameters
-ifn ../synth/example_top.prj
-ifmt mixed
-iuc No
#Target Parameters
-ofn example_top
-ofmt NGC
-p xc6slx45-3csg324
#AXI_ENABLE definition is not required for NATIVE interface
#Source Options
-top example_top
-fsm_extract Yes
-fsm_encoding one-hot
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-shreg_extract Yes
-resource_sharing Yes
-async_to_sync no
-mult_style auto
-register_balancing No
#Target Options
-iobuf Yes
#Max fanout value shouldn't be set below 64 for MCB design
-max_fanout 500
-bufg 16
-register_duplication yes
-optimize_primitives No
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal yes
#General Options
-opt_mode Speed
-opt_level 1
-lso ../synth/example_top.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt allclocknets
-read_cores Yes
-write_timing_constraints No
-cross_clock_analysis No
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-auto_bram_packing No
-slice_utilization_ratio_maxmargin 5
quit

2
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/makeproj.sh vendored Executable file
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NEWPROJECT .
SETPROJECT .

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/mem_interface_top.ut vendored Normal file
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullNone
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g ConfigRate:6

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::****************************************************************************
:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
::
::****************************************************************************
:: ____ ____
:: / /\/ /
:: /___/ \ / Vendor : Xilinx
:: \ \ \/ Version : 3.92
:: \ \ Application : MIG
:: / / Filename : readme.txt
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
:: \ \ / \ Date Created : Fri Feb 06 2009
:: \___\/\___\
::
:: Device : Spartan-6
:: Design Name : DDR/DDR2/DDR3/LPDDR
:: Purpose : Information about par folder
:: Reference :
:: Revision History :
::****************************************************************************
This folder has the batch files to synthesize using XST or Synplify Pro and
implement the design either in "Command Line Mode" or in "GUI Mode".
Steps to run the design using the ise_flow (batch mode):
1. Executing the "ise_flow.bat" file synthesizes the design using XST or
Synplify Pro and does implement the design.
a. First it removes the XST/Synplify Pro report files, implementation
files, supporting scripts, the generated chipscope designs (if
enabled) and the ISE project files (if exist any on previous runs)
b. Synthesizes the design either with XST or Synplicity
c. Implements the design with ISE.
2. After the design is run, it creates ise_flow_results.txt file that will have
the ISE log information.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.bat" file creates "test.xise" project file
and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing the command
'ise test.xise' from the terminal.
Other files in PAR folder :
* "example_top.ucf" file is the constraint file for the design.
It has clock constraints, location constraints and IO standards.
* "mem_interface_top.ut" file has the options for the Configuration file
generation i.e. the "example_top.bit" file to run in batch mode.
* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
implementation files, supporting scripts, the generated chipscope designs
(if enabled) and the ISE project files.
* "set_ise_prop.tcl" file has all the properties that are to be
set in GUI mode.
* "ise_run.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
EDIF/NGC files, you must execute the following commands before starting
synthesis and PAR.
coregen -b ila_coregen.xco
coregen -b icon_coregen.xco
coregen -b vio_coregen.xco
Note : When you generate the design using "Debug Signals for Memory Controller"
option Enable, the above mentioned ChipScope coregen commands are printed
into ise_flow.bat and create_ise.bat files. The example_top rtl file
will have the design debug signals portmapped to vio and icon
ChipScope modules.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "example_top.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "example_top.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
For Multiple Controller designs, signal names provided in CDC file are of
the controller that is enabled for Debug in the GUI.
synth folder:
1. mem_interface_top_synp.sdc
2. script_synp.tcl
3. example_top.prj
4. example_top.lso
mem_interface_top_synp.sdc and script_synp.tcl files are being used by
Synplify Pro and example_top.prj and example_top.lso are being used by XST.

169
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/rem_files.sh vendored Executable file
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##!/bin/csh -f
##****************************************************************************
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.92
## \ \ Application : MIG
## / / Filename : rem_files.bat
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
## \ \ / \ Date Created : Fri Feb 06 2009
## \___\/\___\
##
## Device : Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose : Batch file to remove files generated from ISE
## Reference :
## Revision History :
##****************************************************************************
rm -rf "../synth/__projnav"
rm -rf "../synth/xst"
rm -rf "../synth/_ngo"
rm -rf tmp
rm -rf _xmsgs
rm -rf ila_xdb
rm -rf icon_xdb
rm -rf vio_xdb
rm -rf xlnx_auto_0_xdb
rm -rf vio_xmdf.tcl
rm -rf vio_readme.txt
rm -rf vio_flist.txt
rm -rf vio.xise del
rm -rf vio.xco del
rm -rf vio.ngc del
rm -rf vio.ise del
rm -rf vio.gise del
rm -rf vio.cdc del
rm -rf coregen.cgp
rm -rf coregen.cgc
rm -rf coregen.log
rm -rf ila.cdc
rm -rf ila.gise
rm -rf ila.ise
rm -rf ila.ngc
rm -rf ila.xco
rm -rf ila.xise
rm -rf ila_flist.txt
rm -rf ila_readme.txt
rm -rf ila_xmdf.tcl
rm -rf icon.asy
rm -rf icon.gise
rm -rf icon.ise
rm -rf icon.ncf
rm -rf icon.ngc
rm -rf icon.xco
rm -rf icon.xise
rm -rf icon_flist.txt
rm -rf icon_readme.txt
rm -rf icon_xmdf.tcl
rm -rf ise_flow_results.txt
rm -rf example_top_vhdl.prj
rm -rf mem_interface_top.syr
rm -rf example_top.ngc
rm -rf example_top.ngr
rm -rf example_top_xst.xrpt
rm -rf example_top.bld
rm -rf example_top.ngd
rm -rf example_top_ngdbuild.xrpt
rm -rf example_top_map.map
rm -rf example_top_map.mrp
rm -rf example_top_map.ngm
rm -rf example_top.pcf
rm -rf example_top_map.ncd
rm -rf example_top_map.xrpt
rm -rf example_top_summary.xml
rm -rf example_top_usage.xml
rm -rf example_top.ncd
rm -rf example_top.par
rm -rf example_top.xpi
rm -rf example_top.ptwx
rm -rf example_top.pad
rm -rf example_top.unroutes
rm -rf example_top_pad.csv
rm -rf example_top_pad.txt
rm -rf example_top_par.xrpt
rm -rf example_top.twx
rm -rf example_top.bgn
rm -rf example_top.twr
rm -rf example_top.drc
rm -rf example_top_bitgen.xwbt
rm -rf example_top.bit
# Files and folders generated by create ise
rm -rf test_xdb
rm -rf _xmsgs
rm -rf test.gise
rm -rf test.xise
rm -rf test.xise
# Files and folders generated by ISE through GUI mode
rm -rf _ngo
rm -rf xst
rm -rf example_top.lso
rm -rf example_top.prj
rm -rf example_top.xst
rm -rf example_top.stx
rm -rf example_top_prev_built.ngd
rm -rf test.ntrc_log
rm -rf example_top_guide.ncd
rm -rf example_top.cmd_log
rm -rf example_top_summary.html
rm -rf example_top.ut
rm -rf par_usage_statistics.html
rm -rf usage_statistics_webtalk.html
rm -rf webtalk.log
rm -rf device_usage_statistics.html

106
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/set_ise_prop.tcl vendored Normal file
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project new test.xise
project set "Device Family" "spartan6"
project set "Device" "xc6slx45"
project set "Package" "csg324"
project set "Speed Grade" "-3"
project set "Synthesis Tool" "XST (VHDL/Verilog)"
project set "Simulator" "ISim (VHDL/Verilog)"
xfile add "../rtl/example_top.vhd"
xfile add "../rtl/iodrp_controller.vhd"
xfile add "../rtl/iodrp_mcb_controller.vhd"
xfile add "../rtl/mcb_raw_wrapper.vhd"
xfile add "../rtl/mcb_soft_calibration.vhd"
xfile add "../rtl/mcb_soft_calibration_top.vhd"
xfile add "../rtl/memc3_infrastructure.vhd"
xfile add "../rtl/memc3_tb_top.vhd"
xfile add "../rtl/memc3_wrapper.vhd"
xfile add "../rtl/traffic_gen/afifo.vhd"
xfile add "../rtl/traffic_gen/cmd_gen.vhd"
xfile add "../rtl/traffic_gen/cmd_prbs_gen.vhd"
xfile add "../rtl/traffic_gen/data_prbs_gen.vhd"
xfile add "../rtl/traffic_gen/init_mem_pattern_ctr.vhd"
xfile add "../rtl/traffic_gen/mcb_flow_control.vhd"
xfile add "../rtl/traffic_gen/mcb_traffic_gen.vhd"
xfile add "../rtl/traffic_gen/rd_data_gen.vhd"
xfile add "../rtl/traffic_gen/read_data_path.vhd"
xfile add "../rtl/traffic_gen/read_posted_fifo.vhd"
xfile add "../rtl/traffic_gen/sp6_data_gen.vhd"
xfile add "../rtl/traffic_gen/tg_status.vhd"
xfile add "../rtl/traffic_gen/v6_data_gen.vhd"
xfile add "../rtl/traffic_gen/wr_data_gen.vhd"
xfile add "../rtl/traffic_gen/write_data_path.vhd"
xfile add "example_top.ucf"
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "RAM Extraction" "True" -process "Synthesize - XST"
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "ROM Extraction" "True" -process "Synthesize - XST"
project set "ROM Style" "Auto" -process "Synthesize - XST"
project set "Resource Sharing" "True" -process "Synthesize - XST"
project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Add I/O Buffers" "True" -process "Synthesize - XST"
project set "Max Fanout" "500" -process "Synthesize - XST"
project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
project set "Register Duplication" "True" -process "Synthesize - XST"
project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Library Search Order" "../synth/example_top.lso" -process "Synthesize - XST"
project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Read Cores" "True" -process "Synthesize - XST"
project set "Write Timing Constraints" "False" -process "Synthesize - XST"
project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
project set "Create Binary Configuration File" "False" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
project set "Configuration Rate" "6" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Float" -process "Generate Programming File"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
project set "Drive Done Pin High" "False" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project close

51
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/par/vio_coregen.xco vendored Normal file
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##############################################################
#
# Xilinx Core Generator version 11.2
# Date: Fri Jun 12 05:42:56 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=7
CSET component_name=vio
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
GENERATE
# CRC: 66fe39ed

1059
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/example_top.vhd vendored Normal file
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File diff suppressed because it is too large Load Diff

372
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/iodrp_controller.vhd vendored Executable file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 02/06/09: Initial version for MIG wrapper.
-- 1.1: 02/01/09: updates to indentations.
-- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
-- for state machine always block. Also, assigned
-- intial value to load_shift_n to avoid latch
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues
-- to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
-- added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end entity iodrp_controller;
architecture trans of iodrp_controller is
constant READY : std_logic_vector(2 downto 0) := "000";
constant DECIDE : std_logic_vector(2 downto 0) := "001";
constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(7 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal capture_read_data : std_logic;
signal state : std_logic_vector(2 downto 0);
signal nextstate : std_logic_vector(2 downto 0);
signal data_out_mux : std_logic_vector(7 downto 0);
signal DRP_SDI_pre : std_logic;
signal ALMOST_READY_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
begin
--synthesis translate_off
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY => -- case(state)
-- state_ascii <= "ALMOST_READY";
-- when others =>
-- null;
-- end case;
-- end process;
--synthesis translate_on
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when (state = READY) else '0';
data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
data_reg;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "00000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
-- capture_read_data <= 1'b0;
read_data <= "00000000";
else
-- capture_read_data <= (state == DATA_PHASE);
-- if(capture_read_data)
if (state = ALMOST_READY) then
-- else
-- read_data <= read_data;
read_data <= shift_through_reg;
end if;
end if;
end if;
end process;
ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD <= ADDR_PHASE_ST1;
DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
-- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
-- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the read access.
when ADDR_PHASE =>
if (BIT_CNT7 = '1') then
if (rd_not_write_reg = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
nextstate <= READY;
when others =>
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_soft_calibration_top.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:26 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design top-level simulation
-- wrapper file for input termination calibration
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 2/06/09: Initial version for MIG wrapper.
-- 1.1: 3/16/09: Added pll_lock port, for using it to gate reset
-- 1.2: 6/06/09: Removed MCB_UIDQCOUNT.
-- 1.3: 6/18/09: corrected/changed MCB_SYSRST to be an output port
-- 1.4: 6/24/09: gave RZQ and ZIO each their own unique ADD and SDI nets
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.5: 10/08/09: removed INCDEC_TRESHOLD parameter - making it a localparam inside mcb_soft_calibration
-- 1.6: 02/04/09: Added condition generate statmenet for ZIO pin.
-- 1.7: 04/12/10: Added CKE_Train signal to fix DDR2 init wait .
-- End Revision
--**********************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity mcb_soft_calibration_top is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values,
-- and does dynamic recal,
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY *and*
-- no dynamic recal will be done
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 0; -- provides option to skip the dynamic delay calibration
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR" -- provides the memory device used for the design
);
port (
UI_CLK : in std_logic; -- Input - global clock to be used for input_term_tuner and IODRP clock
RST : in std_logic; -- Input - reset for input_term_tuner - synchronous for input_term_tuner state machine, asynch for
-- IODRP (sub)controller
IOCLK : in std_logic; -- Input - IOCLK input to the IODRP's
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high
-- (MCB hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic;
MCB_UODONECAL : in std_logic;
MCB_UOREFRSHFLAG : in std_logic;
MCB_UICS : out std_logic;
MCB_UIDRPUPDATE : out std_logic;
MCB_UIBROADCAST : out std_logic;
MCB_UIADDR : out std_logic_vector(4 downto 0);
MCB_UICMDEN : out std_logic;
MCB_UIDONECAL : out std_logic;
MCB_UIDQLOWERDEC : out std_logic;
MCB_UIDQLOWERINC : out std_logic;
MCB_UIDQUPPERDEC : out std_logic;
MCB_UIDQUPPERINC : out std_logic;
MCB_UILDQSDEC : out std_logic;
MCB_UILDQSINC : out std_logic;
MCB_UIREAD : out std_logic;
MCB_UIUDQSDEC : out std_logic;
MCB_UIUDQSINC : out std_logic;
MCB_RECAL : out std_logic;
MCB_SYSRST : out std_logic;
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
RZQ_PIN : inout std_logic;
ZIO_PIN : inout std_logic;
CKE_Train : out std_logic
);
end entity mcb_soft_calibration_top;
architecture trans of mcb_soft_calibration_top is
component mcb_soft_calibration is
generic (
C_MEM_TZQINIT_MAXCNT : std_logic_vector(9 downto 0) := "1000000000"; -- DDR3 Minimum delay between resets
SKIP_IN_TERM_CAL : integer := 0; -- provides option to skip the input termination calibration
SKIP_DYNAMIC_CAL : integer := 0; -- provides option to skip the dynamic delay calibration
SKIP_DYN_IN_TERM : integer := 1; -- provides option to skip the input termination calibration
C_MC_CALIBRATION_MODE : string := "CALIBRATION"; -- if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param value
-- if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY
-- (Quarter, etc)
C_SIMULATION : string := "FALSE"; -- Tells us whether the design is being simulated or implemented
C_MEM_TYPE : string := "DDR"
);
port (
UI_CLK : in std_logic; -- main clock input for logic and IODRP CLK pins. At top level, this should also connect to IODRP2_MCB
-- CLK pins
RST : in std_logic; -- main system reset for both the Soft Calibration block - also will act as a passthrough to MCB's SYSRST
DONE_SOFTANDHARD_CAL : out std_logic; -- active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB
-- hard calib complete)
PLL_LOCK : in std_logic; -- Lock signal from PLL
SELFREFRESH_REQ : in std_logic;
SELFREFRESH_MCB_MODE : in std_logic;
SELFREFRESH_MCB_REQ : out std_logic;
SELFREFRESH_MODE : out std_logic;
IODRP_ADD : out std_logic; -- IODRP ADD port
IODRP_SDI : out std_logic; -- IODRP SDI port
RZQ_IN : in std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
RZQ_IODRP_SDO : in std_logic; -- RZQ IODRP's SDO port
RZQ_IODRP_CS : out std_logic := '0'; -- RZQ IODRP's CS port
ZIO_IN : in std_logic; -- Z-stated IO pin - garanteed not to be driven externally
ZIO_IODRP_SDO : in std_logic; -- ZIO IODRP's SDO port
ZIO_IODRP_CS : out std_logic := '0'; -- ZIO IODRP's CS port
MCB_UIADD : out std_logic; -- to MCB's UIADD port
MCB_UISDI : out std_logic; -- to MCB's UISDI port
MCB_UOSDO : in std_logic; -- from MCB's UOSDO port (User output SDO)
MCB_UODONECAL : in std_logic; -- indicates when MCB hard calibration process is complete
MCB_UOREFRSHFLAG : in std_logic; -- high during refresh cycle and time when MCB is innactive
MCB_UICS : out std_logic; -- to MCB's UICS port (User Input CS)
MCB_UIDRPUPDATE : out std_logic := '1'; -- MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used
-- during IODRP2_MCB writes). Currently just trasnparent
MCB_UIBROADCAST : out std_logic; -- only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)
MCB_UIADDR : out std_logic_vector(4 downto 0) := "00000"; -- to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port
MCB_UICMDEN : out std_logic := '1'; -- set to 1 to take control of UI interface - removes control from internal calib block
MCB_UIDONECAL : out std_logic := '0'; -- set to 0 to "tell" controller that it's still in a calibrate state
MCB_UIDQLOWERDEC : out std_logic := '0';
MCB_UIDQLOWERINC : out std_logic := '0';
MCB_UIDQUPPERDEC : out std_logic := '0';
MCB_UIDQUPPERINC : out std_logic := '0';
MCB_UILDQSDEC : out std_logic := '0';
MCB_UILDQSINC : out std_logic := '0';
MCB_UIREAD : out std_logic; -- enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in
-- regular IODRP2). IODRPCTRLR_R_WB becomes don't-care.
MCB_UIUDQSDEC : out std_logic := '0';
MCB_UIUDQSINC : out std_logic := '0';
MCB_RECAL : out std_logic := '0'; -- future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high
MCB_UICMD : out std_logic;
MCB_UICMDIN : out std_logic;
MCB_UIDQCOUNT : out std_logic_vector(3 downto 0);
MCB_UODATA : in std_logic_vector(7 downto 0);
MCB_UODATAVALID : in std_logic;
MCB_UOCMDREADY : in std_logic;
MCB_UO_CAL_START : in std_logic;
MCB_SYSRST : out std_logic; -- drives the MCB's SYSRST pin - the main reset for MCB
Max_Value : out std_logic_vector(7 downto 0);
CKE_Train : out std_logic
);
end component;
signal IODRP_ADD : std_logic;
signal IODRP_SDI : std_logic;
signal RZQ_IODRP_SDO : std_logic;
signal RZQ_IODRP_CS : std_logic;
signal ZIO_IODRP_SDO : std_logic;
signal ZIO_IODRP_CS : std_logic;
signal IODRP_SDO : std_logic;
signal IODRP_CS : std_logic;
signal IODRP_BKST : std_logic;
signal RZQ_ZIO_ODATAIN : std_logic;
signal RZQ_ZIO_TRISTATE : std_logic;
signal RZQ_TOUT : std_logic;
signal ZIO_TOUT : std_logic;
signal Max_Value : std_logic_vector(7 downto 0);
signal RZQ_IN : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R1 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal RZQ_IN_R2 : std_logic; -- RZQ pin from board - expected to have a 2*R resistor to ground
signal ZIO_IN : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R1 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal ZIO_IN_R2 : std_logic; -- Z-stated IO pin - garanteed not to be driven externally
signal RZQ_OUT : std_logic;
signal ZIO_OUT : std_logic;
-- Declare intermediate signals for referenced outputs
signal DONE_SOFTANDHARD_CAL_xilinx0 : std_logic;
signal MCB_UIADD_xilinx3 : std_logic;
signal MCB_UISDI_xilinx17 : std_logic;
signal MCB_UICS_xilinx7 : std_logic;
signal MCB_UIDRPUPDATE_xilinx13 : std_logic;
signal MCB_UIBROADCAST_xilinx5 : std_logic;
signal MCB_UIADDR_xilinx4 : std_logic_vector(4 downto 0);
signal MCB_UICMDEN_xilinx6 : std_logic;
signal MCB_UIDONECAL_xilinx8 : std_logic;
signal MCB_UIDQLOWERDEC_xilinx9 : std_logic;
signal MCB_UIDQLOWERINC_xilinx10 : std_logic;
signal MCB_UIDQUPPERDEC_xilinx11 : std_logic;
signal MCB_UIDQUPPERINC_xilinx12 : std_logic;
signal MCB_UILDQSDEC_xilinx14 : std_logic;
signal MCB_UILDQSINC_xilinx15 : std_logic;
signal MCB_UIREAD_xilinx16 : std_logic;
signal MCB_UIUDQSDEC_xilinx18 : std_logic;
signal MCB_UIUDQSINC_xilinx19 : std_logic;
signal MCB_RECAL_xilinx1 : std_logic;
signal MCB_SYSRST_xilinx2 : std_logic;
begin
-- Drive referenced outputs
DONE_SOFTANDHARD_CAL <= DONE_SOFTANDHARD_CAL_xilinx0;
MCB_UIADD <= MCB_UIADD_xilinx3;
MCB_UISDI <= MCB_UISDI_xilinx17;
MCB_UICS <= MCB_UICS_xilinx7;
MCB_UIDRPUPDATE <= MCB_UIDRPUPDATE_xilinx13;
MCB_UIBROADCAST <= MCB_UIBROADCAST_xilinx5;
MCB_UIADDR <= MCB_UIADDR_xilinx4;
MCB_UICMDEN <= MCB_UICMDEN_xilinx6;
MCB_UIDONECAL <= MCB_UIDONECAL_xilinx8;
MCB_UIDQLOWERDEC <= MCB_UIDQLOWERDEC_xilinx9;
MCB_UIDQLOWERINC <= MCB_UIDQLOWERINC_xilinx10;
MCB_UIDQUPPERDEC <= MCB_UIDQUPPERDEC_xilinx11;
MCB_UIDQUPPERINC <= MCB_UIDQUPPERINC_xilinx12;
MCB_UILDQSDEC <= MCB_UILDQSDEC_xilinx14;
MCB_UILDQSINC <= MCB_UILDQSINC_xilinx15;
MCB_UIREAD <= MCB_UIREAD_xilinx16;
MCB_UIUDQSDEC <= MCB_UIUDQSDEC_xilinx18;
MCB_UIUDQSINC <= MCB_UIUDQSINC_xilinx19;
MCB_RECAL <= MCB_RECAL_xilinx1;
MCB_SYSRST <= MCB_SYSRST_xilinx2;
RZQ_ZIO_ODATAIN <= not(RST);
RZQ_ZIO_TRISTATE <= not(RST);
IODRP_BKST <= '0'; -- future hook for possible BKST to ZIO and RZQ
mcb_soft_calibration_inst : mcb_soft_calibration
generic map (
C_MEM_TZQINIT_MAXCNT => C_MEM_TZQINIT_MAXCNT,
C_MC_CALIBRATION_MODE => C_MC_CALIBRATION_MODE,
SKIP_IN_TERM_CAL => SKIP_IN_TERM_CAL,
SKIP_DYNAMIC_CAL => SKIP_DYNAMIC_CAL,
SKIP_DYN_IN_TERM => SKIP_DYN_IN_TERM,
C_SIMULATION => C_SIMULATION,
C_MEM_TYPE => C_MEM_TYPE
)
port map (
UI_CLK => UI_CLK,
RST => RST,
PLL_LOCK => PLL_LOCK,
SELFREFRESH_REQ => SELFREFRESH_REQ,
SELFREFRESH_MCB_MODE => SELFREFRESH_MCB_MODE,
SELFREFRESH_MCB_REQ => SELFREFRESH_MCB_REQ,
SELFREFRESH_MODE => SELFREFRESH_MODE,
DONE_SOFTANDHARD_CAL => DONE_SOFTANDHARD_CAL_xilinx0,
IODRP_ADD => IODRP_ADD,
IODRP_SDI => IODRP_SDI,
RZQ_IN => RZQ_IN_R2,
RZQ_IODRP_SDO => RZQ_IODRP_SDO,
RZQ_IODRP_CS => RZQ_IODRP_CS,
ZIO_IN => ZIO_IN_R2,
ZIO_IODRP_SDO => ZIO_IODRP_SDO,
ZIO_IODRP_CS => ZIO_IODRP_CS,
MCB_UIADD => MCB_UIADD_xilinx3,
MCB_UISDI => MCB_UISDI_xilinx17,
MCB_UOSDO => MCB_UOSDO,
MCB_UODONECAL => MCB_UODONECAL,
MCB_UOREFRSHFLAG => MCB_UOREFRSHFLAG,
MCB_UICS => MCB_UICS_xilinx7,
MCB_UIDRPUPDATE => MCB_UIDRPUPDATE_xilinx13,
MCB_UIBROADCAST => MCB_UIBROADCAST_xilinx5,
MCB_UIADDR => MCB_UIADDR_xilinx4,
MCB_UICMDEN => MCB_UICMDEN_xilinx6,
MCB_UIDONECAL => MCB_UIDONECAL_xilinx8,
MCB_UIDQLOWERDEC => MCB_UIDQLOWERDEC_xilinx9,
MCB_UIDQLOWERINC => MCB_UIDQLOWERINC_xilinx10,
MCB_UIDQUPPERDEC => MCB_UIDQUPPERDEC_xilinx11,
MCB_UIDQUPPERINC => MCB_UIDQUPPERINC_xilinx12,
MCB_UILDQSDEC => MCB_UILDQSDEC_xilinx14,
MCB_UILDQSINC => MCB_UILDQSINC_xilinx15,
MCB_UIREAD => MCB_UIREAD_xilinx16,
MCB_UIUDQSDEC => MCB_UIUDQSDEC_xilinx18,
MCB_UIUDQSINC => MCB_UIUDQSINC_xilinx19,
MCB_RECAL => MCB_RECAL_xilinx1,
MCB_UICMD => MCB_UICMD,
MCB_UICMDIN => MCB_UICMDIN,
MCB_UIDQCOUNT => MCB_UIDQCOUNT,
MCB_UODATA => MCB_UODATA,
MCB_UODATAVALID => MCB_UODATAVALID,
MCB_UOCMDREADY => MCB_UOCMDREADY,
MCB_UO_CAL_START => MCB_UO_CAL_START,
mcb_sysrst => MCB_SYSRST_xilinx2,
Max_Value => Max_Value,
CKE_Train => CKE_Train
);
process(UI_CLK,RST)
begin
if (RST = '1') then
ZIO_IN_R1 <= '0';
ZIO_IN_R2 <= '0';
RZQ_IN_R1 <= '0';
RZQ_IN_R2 <= '0';
elsif (UI_CLK'event and UI_CLK = '1') then
ZIO_IN_R1 <= ZIO_IN;
ZIO_IN_R2 <= ZIO_IN_R1;
RZQ_IN_R1 <= RZQ_IN;
RZQ_IN_R2 <= RZQ_IN_R1;
end if;
end process;
IOBUF_RZQ : IOBUF
port map (
o => RZQ_IN,
io => RZQ_PIN,
i => RZQ_OUT,
t => RZQ_TOUT
);
IODRP2_RZQ : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => RZQ_OUT,
sdo => RZQ_IODRP_SDO,
tout => RZQ_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => RZQ_IODRP_CS,
idatain => RZQ_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
gen_zio: if ( ((C_MEM_TYPE = "DDR") or (C_MEM_TYPE = "DDR2") or (C_MEM_TYPE = "DDR3")) and
(SKIP_IN_TERM_CAL = 0)) generate
IOBUF_ZIO : IOBUF
port map (
o => ZIO_IN,
io => ZIO_PIN,
i => ZIO_OUT,
t => ZIO_TOUT
);
IODRP2_ZIO : IODRP2
port map (
dataout => open,
dataout2 => open,
dout => ZIO_OUT,
sdo => ZIO_IODRP_SDO,
tout => ZIO_TOUT,
add => IODRP_ADD,
bkst => IODRP_BKST,
clk => UI_CLK,
cs => ZIO_IODRP_CS,
idatain => ZIO_IN,
ioclk0 => IOCLK,
ioclk1 => '1',
odatain => RZQ_ZIO_ODATAIN,
sdi => IODRP_SDI,
t => RZQ_ZIO_TRISTATE
);
end generate;
end architecture trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : memc3_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : Clock generation/distribution and reset synchronization
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity memc3_infrastructure is
generic
(
C_INCLK_PERIOD : integer := 2500;
C_RST_ACT_LOW : integer := 1;
C_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
C_DIVCLK_DIVIDE : integer := 1
);
port
(
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
mcb_drp_clk : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic
);
end entity;
architecture syn of memc3_infrastructure is
-- # of clock cycles to delay deassertion of reset. Needs to be a fairly
-- high number not so much for metastability protection, but to give time
-- for reset (i.e. stable clock cycles) to propagate through all state
-- machines and to all control signals (i.e. not all control signals have
-- resets, instead they rely on base state logic being reset, and the effect
-- of that reset propagating through the logic). Need this because we may not
-- be getting stable clock cycles while reset asserted (i.e. since reset
-- depends on PLL/DCM lock status)
constant RST_SYNC_NUM : integer := 25;
constant CLK_PERIOD_NS : real := (real(C_INCLK_PERIOD)) / 1000.0;
constant CLK_PERIOD_INT : integer := C_INCLK_PERIOD/1000;
signal clk_2x_0 : std_logic;
signal clk_2x_180 : std_logic;
signal clk0_bufg : std_logic;
signal clk0_bufg_in : std_logic;
signal mcb_drp_clk_bufg_in : std_logic;
signal clkfbout_clkfbin : std_logic;
signal rst_tmp : std_logic;
signal sys_clk_ibufg : std_logic;
signal sys_rst : std_logic;
signal rst0_sync_r : std_logic_vector(RST_SYNC_NUM-1 downto 0);
signal powerup_pll_locked : std_logic;
signal syn_clk0_powerup_pll_locked : std_logic;
signal locked : std_logic;
signal bufpll_mcb_locked : std_logic;
signal mcb_drp_clk_sig : std_logic;
attribute max_fanout : string;
attribute syn_maxfan : integer;
attribute KEEP : string;
attribute max_fanout of rst0_sync_r : signal is "10";
attribute syn_maxfan of rst0_sync_r : signal is 10;
attribute KEEP of sys_clk_ibufg : signal is "TRUE";
begin
sys_rst <= not(sys_rst_i) when (C_RST_ACT_LOW /= 0) else sys_rst_i;
clk0 <= clk0_bufg;
pll_lock <= bufpll_mcb_locked;
mcb_drp_clk <= mcb_drp_clk_sig;
diff_input_clk : if(C_INPUT_CLK_TYPE = "DIFFERENTIAL") generate
--***********************************************************************
-- Differential input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
I => sys_clk_p,
IB => sys_clk_n,
O => sys_clk_ibufg
);
end generate;
se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
u_ibufg_sys_clk : IBUFG
port map (
I => sys_clk,
O => sys_clk_ibufg
);
end generate;
--***************************************************************************
-- Global clock generation and distribution
--***************************************************************************
u_pll_adv : PLL_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => CLK_PERIOD_NS,
CLKIN2_PERIOD => CLK_PERIOD_NS,
CLKOUT0_DIVIDE => C_CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE => C_CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE => C_CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE => C_CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 180.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
SIM_DEVICE => "SPARTAN6",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => C_DIVCLK_DIVIDE,
CLKFBOUT_MULT => C_CLKFBOUT_MULT,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000
)
port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk_ibufg,
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);
U_BUFG_CLK0 : BUFG
port map
(
O => clk0_bufg,
I => clk0_bufg_in
);
--U_BUFG_CLK1 : BUFG
-- port map (
-- O => mcb_drp_clk_sig,
-- I => mcb_drp_clk_bufg_in
-- );
U_BUFG_CLK1 : BUFGCE
port map (
O => mcb_drp_clk_sig,
I => mcb_drp_clk_bufg_in,
CE => locked
);
process (mcb_drp_clk_sig, sys_rst)
begin
if(sys_rst = '1') then
powerup_pll_locked <= '0';
elsif (mcb_drp_clk_sig'event and mcb_drp_clk_sig = '1') then
if (bufpll_mcb_locked = '1') then
powerup_pll_locked <= '1';
end if;
end if;
end process;
process (clk0_bufg, sys_rst)
begin
if(sys_rst = '1') then
syn_clk0_powerup_pll_locked <= '0';
elsif (clk0_bufg'event and clk0_bufg = '1') then
if (bufpll_mcb_locked = '1') then
syn_clk0_powerup_pll_locked <= '1';
end if;
end if;
end process;
--***************************************************************************
-- Reset synchronization
-- NOTES:
-- 1. shut down the whole operation if the PLL hasn't yet locked (and
-- by inference, this means that external sys_rst has been asserted -
-- PLL deasserts LOCKED as soon as sys_rst asserted)
-- 2. asynchronously assert reset. This was we can assert reset even if
-- there is no clock (needed for things like 3-stating output buffers).
-- reset deassertion is synchronous.
-- 3. asynchronous reset only look at pll_lock from PLL during power up. After
-- power up and pll_lock is asserted, the powerup_pll_locked will be asserted
-- forever until sys_rst is asserted again. PLL will lose lock when FPGA
-- enters suspend mode. We don't want reset to MCB get
-- asserted in the application that needs suspend feature.
--***************************************************************************
async_rst <= sys_rst or not(powerup_pll_locked);
-- async_rst <= rst_tmp;
rst_tmp <= sys_rst or not(syn_clk0_powerup_pll_locked);
-- rst_tmp <= sys_rst or not(powerup_pll_locked);
process (clk0_bufg, rst_tmp)
begin
if (rst_tmp = '1') then
rst0_sync_r <= (others => '1');
elsif (rising_edge(clk0_bufg)) then
rst0_sync_r <= rst0_sync_r(RST_SYNC_NUM-2 downto 0) & '0'; -- logical left shift by one (pads with 0)
end if;
end process;
rst0 <= rst0_sync_r(RST_SYNC_NUM-1);
BUFPLL_MCB_INST : BUFPLL_MCB
port map
( IOCLK0 => sysclk_2x,
IOCLK1 => sysclk_2x_180,
LOCKED => locked,
GCLK => mcb_drp_clk_sig,
SERDESSTROBE0 => pll_ce_0,
SERDESSTROBE1 => pll_ce_90,
PLLIN0 => clk_2x_0,
PLLIN1 => clk_2x_180,
LOCK => bufpll_mcb_locked
);
end architecture syn;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: afifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:34 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: A generic synchronous fifo.
-- Reference:
-- Revision History: 2009/01/09 corrected signal "buf_avail" and "almost_full" equation.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
ENTITY afifo IS
GENERIC (
TCQ : TIME := 100 ps;
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 4;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC
);
END afifo;
ARCHITECTURE trans OF afifo IS
TYPE mem_array IS ARRAY (0 TO FIFO_DEPTH ) OF STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
SIGNAL mem : mem_array;
SIGNAL rd_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_gray_nxt : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL pre_wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_capture_gray_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_avail : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL buf_filled : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wr_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL rd_addr : STD_LOGIC_VECTOR(ASIZE - 1 DOWNTO 0);
SIGNAL wr_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL rd_ptr : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL i : INTEGER;
SIGNAL j : INTEGER;
SIGNAL k : INTEGER;
SIGNAL rd_strobe : STD_LOGIC;
SIGNAL n : INTEGER;
SIGNAL rd_ptr_tmp : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbin : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wgraynext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL wbinnext : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ZERO : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
SIGNAL ONE : STD_LOGIC_VECTOR(ASIZE DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL full_xhdl1 : STD_LOGIC;
SIGNAL almost_full_int : STD_LOGIC;
SIGNAL empty_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
ZERO <= std_logic_vector(to_unsigned(0,(ASIZE+1)));
ONE <= std_logic_vector(to_unsigned(1,(ASIZE+1)));
full <= full_xhdl1;
empty <= empty_xhdl0;
xhdl3 : IF (SYNC = 1) GENERATE
PROCESS (rd_ptr)
BEGIN
rd_capture_ptr <= rd_ptr;
END PROCESS;
END GENERATE;
xhdl4 : IF (SYNC = 1) GENERATE
PROCESS (wr_ptr)
BEGIN
wr_capture_ptr <= wr_ptr;
END PROCESS;
END GENERATE;
wr_addr <= wr_ptr(ASIZE-1 DOWNTO 0);
rd_data <= mem(conv_integer(rd_addr));
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF ((wr_en AND NOT(full_xhdl1)) = '1') THEN
mem(to_integer(unsigned(wr_addr))) <= wr_data;
END IF;
END IF;
END PROCESS;
rd_addr <= rd_ptr(ASIZE - 1 DOWNTO 0);
rd_strobe <= rd_en AND NOT(empty_xhdl0);
PROCESS (rd_ptr)
BEGIN
rd_gray_nxt(ASIZE) <= rd_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
rd_gray_nxt(n) <= rd_ptr(n) XOR rd_ptr(n + 1);
END LOOP;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
rd_ptr <= (others=> '0');
rd_gray <= (others=> '0');
ELSE
IF (rd_strobe = '1') THEN
rd_ptr <= rd_ptr + 1;
END IF;
rd_ptr_tmp <= rd_ptr;
rd_gray <= rd_gray_nxt;
END IF;
END IF;
END PROCESS;
buf_filled <= wr_capture_ptr - rd_ptr;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
empty_xhdl0 <= '1';
ELSIF ((buf_filled = ZERO) OR (buf_filled = ONE AND rd_strobe = '1')) THEN
empty_xhdl0 <= '1';
ELSE
empty_xhdl0 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (rd_clk)
BEGIN
IF (rd_clk'EVENT AND rd_clk = '1') THEN
IF (rst = '1') THEN
wr_ptr <= (others => '0');
wr_gray <= (others => '0');
ELSE
IF (wr_en = '1') THEN
wr_ptr <= wr_ptr + 1;
END IF;
wr_gray <= wr_gray_nxt;
END IF;
END IF;
END PROCESS;
PROCESS (wr_ptr)
BEGIN
wr_gray_nxt(ASIZE) <= wr_ptr(ASIZE);
FOR n IN 0 TO ASIZE - 1 LOOP
wr_gray_nxt(n) <= wr_ptr(n) XOR wr_ptr(n + 1);
END LOOP;
END PROCESS;
buf_avail <= rd_capture_ptr + FIFO_DEPTH - wr_ptr;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
full_xhdl1 <= '0';
ELSIF ((buf_avail = ZERO) OR (buf_avail = ONE AND wr_en = '1')) THEN
full_xhdl1 <= '1';
ELSE
full_xhdl1 <= '0';
END IF;
END IF;
END PROCESS;
almost_full <= almost_full_int;
PROCESS (wr_clk)
BEGIN
IF (wr_clk'EVENT AND wr_clk = '1') THEN
IF (rst = '1') THEN
almost_full_int <= '0';
ELSIF (buf_avail <= 3 AND wr_en = '1') THEN --FIFO_DEPTH
almost_full_int <= '1';
ELSE
almost_full_int <= '0';
END IF;
END IF;
END PROCESS;
END trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: cmd_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:37 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel use LFSR to generate random address, isntructions
-- or burst_length.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY cmd_prbs_gen IS
GENERIC (
TCQ : time := 100 ps;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 29;
DWIDTH : INTEGER := 32;
PRBS_CMD : STRING := "ADDRESS";
PRBS_WIDTH : INTEGER := 64;
SEED_WIDTH : INTEGER := 32;
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"FFFFD000";
PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00002000";
PRBS_EADDR : std_logic_vector(31 downto 0) := X"00002000";
PRBS_SADDR : std_logic_vector(31 downto 0) := X"00002000"
);
PORT (
clk_i : IN STD_LOGIC;
prbs_seed_init : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0)
);
END cmd_prbs_gen;
ARCHITECTURE trans OF cmd_prbs_gen IS
SIGNAL ZEROS : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
SIGNAL prbs : STD_LOGIC_VECTOR(SEED_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
function logb2 (val : integer) return integer is
variable vec_con : integer;
variable rtn : integer := 1;
begin
vec_con := val;
for index in 0 to 31 loop
if(vec_con = 1) then
rtn := rtn + 1;
return(rtn);
end if;
vec_con := vec_con/2;
rtn := rtn + 1;
end loop;
end function logb2;
BEGIN
ZEROS <= std_logic_vector(to_unsigned(0,ADDR_WIDTH));
xhdl0 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 64) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ('0' & ("0000000000000000000000000000000" & prbs_seed_i)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(64) <= lfsr_q(64) XOR lfsr_q(63) ;
lfsr_q(63) <= lfsr_q(62) ;
lfsr_q(62) <= lfsr_q(64) XOR lfsr_q(61) ;
lfsr_q(61) <= lfsr_q(64) XOR lfsr_q(60) ;
lfsr_q(60 DOWNTO 2) <= lfsr_q(59 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(64) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
prbs <= lfsr_q(32 DOWNTO 1);
END PROCESS;
END GENERATE;
xhdl1 : IF (PRBS_CMD = "ADDRESS" AND PRBS_WIDTH = 32) GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= prbs_seed_i ;
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8) ;
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7) ;
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6) ;
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3) ;
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2) ;
lfsr_q(2) <= lfsr_q(1) ;
lfsr_q(1) <= lfsr_q(32) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(32 DOWNTO 1))
BEGIN
IF (FAMILY = "SPARTAN6") THEN
FOR i IN (logb2(DWIDTH) + 1) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
ELSE
FOR i IN (logb2(DWIDTH) - 4) TO SEED_WIDTH - 1 LOOP
IF (PRBS_SADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_SADDR(i) OR lfsr_q(i + 1);
ELSIF (PRBS_EADDR_MASK_POS(i) = '1') THEN
prbs(i) <= PRBS_EADDR(i) AND lfsr_q(i + 1);
ELSE
prbs(i) <= lfsr_q(i + 1);
END IF;
END LOOP;
prbs(logb2(DWIDTH) downto 0) <= (others => '0');
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (PRBS_CMD = "INSTR" OR PRBS_CMD = "BLEN") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (prbs_seed_init = '1') THEN
lfsr_q <= ("00000" & prbs_seed_i(14 DOWNTO 0)) ;
ELSIF (clk_en = '1') THEN
lfsr_q(20) <= lfsr_q(19) ;
lfsr_q(19) <= lfsr_q(18) ;
lfsr_q(18) <= lfsr_q(20) XOR lfsr_q(17) ;
lfsr_q(17 DOWNTO 2) <= lfsr_q(16 DOWNTO 1) ;
lfsr_q(1) <= lfsr_q(20) ;
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(SEED_WIDTH - 1 DOWNTO 1), ZEROS)
BEGIN
prbs <= (ZEROS(SEED_WIDTH - 1 DOWNTO 6) & lfsr_q(6 DOWNTO 1));
END PROCESS;
END GENERATE;
prbs_o <= prbs;
END trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: data_prbs_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is used LFSR to generate random data for memory
-- data write or memory data read comparison.The first data is
-- seeded by the input prbs_seed_i which is connected to memory address.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
-- TAPS : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0) := "10000000001000000000000001100010"
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END data_prbs_gen;
ARCHITECTURE trans OF data_prbs_gen IS
SIGNAL prbs : STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
SIGNAL lfsr_q : STD_LOGIC_VECTOR(PRBS_WIDTH DOWNTO 1);
SIGNAL i : INTEGER;
BEGIN
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((prbs_seed_init = '1') AND (EYE_TEST = "FALSE")) OR (rst_i = '1')) THEN
lfsr_q <= prbs_seed_i + prbs_fseed_i(31 DOWNTO 0) + "01010101010101010101010101010101";
ELSIF (clk_en = '1') THEN
lfsr_q(32 DOWNTO 9) <= lfsr_q(31 DOWNTO 8);
lfsr_q(8) <= lfsr_q(32) XOR lfsr_q(7);
lfsr_q(7) <= lfsr_q(32) XOR lfsr_q(6);
lfsr_q(6 DOWNTO 4) <= lfsr_q(5 DOWNTO 3);
lfsr_q(3) <= lfsr_q(32) XOR lfsr_q(2);
lfsr_q(2) <= lfsr_q(1);
lfsr_q(1) <= lfsr_q(32);
END IF;
END IF;
END PROCESS;
PROCESS (lfsr_q(PRBS_WIDTH DOWNTO 1))
BEGIN
prbs <= lfsr_q(PRBS_WIDTH DOWNTO 1);
END PROCESS;
prbs_o <= prbs;
END trans;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/init_mem_pattern_ctr.vhd vendored Executable file
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@@ -0,0 +1,620 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: init_mem_pattern_ctr.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:39 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This moduel has a small FSM to control the operation of
-- mcb_traffic_gen module.It first fill up the memory with a selected
-- DATA pattern and then starts the memory testing state.
-- Reference:
-- Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
-- and the fixed_bl_o is fixed at 64 if data_mode_o == PRBS and FAMILY == "SPARTAN6"
-- The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
-- 1.2 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
-- "OTF" Burst Mode and TG will only generate BL 8 traffic.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY init_mem_pattern_ctr IS
GENERIC (
FAMILY : STRING := "SPARTAN6";
TST_MEM_INSTR_MODE : STRING := "R_W_INSTR_MODE";
MEM_BURST_LEN : INTEGER := 8;
CMD_PATTERN : STRING := "CGEN_ALL";
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
CMD_SEED_VALUE : std_logic_vector(31 downto 0) := X"12345678";
DATA_SEED_VALUE : std_logic_vector(31 downto 0) := X"ca345675";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
PORT_MODE : STRING := "BI_MODE";
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
mcb_cmd_bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_en_i : IN STD_LOGIC;
mcb_cmd_instr_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
mcb_wr_en_i : IN STD_LOGIC;
vio_modify_enable : IN STD_LOGIC;
vio_data_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_addr_mode_value : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
vio_bl_mode_value : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
vio_fixed_bl_value : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_init_done_i : IN STD_LOGIC;
cmp_error : IN STD_LOGIC;
run_traffic_o : OUT STD_LOGIC;
start_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
end_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cmd_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
data_seed_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
load_seed_o : OUT STD_LOGIC;
addr_mode_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
instr_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bl_mode_o : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
data_mode_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
mode_load_o : OUT STD_LOGIC;
fixed_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
fixed_instr_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
fixed_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END init_mem_pattern_ctr;
ARCHITECTURE trans OF init_mem_pattern_ctr IS
constant IDLE : std_logic_vector(4 downto 0) := "00001";
constant INIT_MEM_WRITE : std_logic_vector(4 downto 0) := "00010";
constant INIT_MEM_READ : std_logic_vector(4 downto 0) := "00100";
constant TEST_MEM : std_logic_vector(4 downto 0) := "01000";
constant CMP_ERROR1 : std_logic_vector(4 downto 0) := "10000";
constant BRAM_ADDR : std_logic_vector(1 downto 0) := "00";
constant FIXED_ADDR : std_logic_vector(2 downto 0) := "001";
constant PRBS_ADDR : std_logic_vector(2 downto 0) := "010";
constant SEQUENTIAL_ADDR : std_logic_vector(2 downto 0) := "011";
constant BRAM_INSTR_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_INSTR_MODE : std_logic_vector(3 downto 0) := "0001";
constant FIXED_INSTR_MODE_WITH_REFRESH : std_logic_vector(3 downto 0) := "0110";
constant R_W_INSTR_MODE : std_logic_vector(3 downto 0) := "0010";
constant RP_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0011";
constant R_RP_W_WP_INSTR_MODE : std_logic_vector(3 downto 0) := "0100";
constant R_RP_W_WP_REF_INSTR_MODE : std_logic_vector(3 downto 0) := "0101";
constant BRAM_BL_MODE : std_logic_vector(1 downto 0) := "00";
constant FIXED_BL_MODE : std_logic_vector(1 downto 0) := "01";
constant PRBS_BL_MODE : std_logic_vector(1 downto 0) := "10";
constant BRAM_DATAL_MODE : std_logic_vector(3 downto 0) := "0000";
constant FIXED_DATA_MODE : std_logic_vector(3 downto 0) := "0001";
constant ADDR_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant HAMMER_DATA_MODE : std_logic_vector(3 downto 0) := "0011";
constant NEIGHBOR_DATA_MODE : std_logic_vector(3 downto 0) := "0100";
constant WALKING1_DATA_MODE : std_logic_vector(3 downto 0) := "0101";
constant WALKING0_DATA_MODE : std_logic_vector(3 downto 0) := "0110";
constant PRBS_DATA_MODE : std_logic_vector(3 downto 0) := "0111";
constant RD_INSTR : std_logic_vector(2 downto 0) := "001";
constant RDP_INSTR : std_logic_vector(2 downto 0) := "011";
constant WR_INSTR : std_logic_vector(2 downto 0) := "000";
constant WRP_INSTR : std_logic_vector(2 downto 0) := "010";
constant REFRESH_INSTR : std_logic_vector(2 downto 0) := "100";
constant NOP_WR_INSTR : std_logic_vector(2 downto 0) := "101";
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL mcb_init_done_reg : STD_LOGIC;
SIGNAL mcb_init_done_reg1 : STD_LOGIC;
SIGNAL AC2_G_E2 : STD_LOGIC;
SIGNAL AC1_G_E1 : STD_LOGIC;
SIGNAL AC3_G_E3 : STD_LOGIC;
SIGNAL upper_end_matched : STD_LOGIC;
SIGNAL end_boundary_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL mcb_cmd_en_r : STD_LOGIC;
SIGNAL mcb_cmd_bl_r : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL lower_end_matched : STD_LOGIC;
SIGNAL end_addr_reached : STD_LOGIC;
SIGNAL run_traffic : STD_LOGIC;
SIGNAL current_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL fix_bl_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL data_mode_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL addr_mode_sel : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL bl_mode_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL addr_mode : STD_LOGIC_VECTOR(2 DOWNTO 0);
-- SIGNAL data_mode1 : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL INC_COUNTS : STD_LOGIC_VECTOR(10 DOWNTO 0);
SIGNAL FIXEDBL : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL FIXED_BL_VALUE : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL bram_mode_enable : STD_LOGIC;
SIGNAL syn1_vio_data_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL syn1_vio_addr_mode_value : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_mem_instr_mode : STD_LOGIC_VECTOR(3 DOWNTO 0);
-- Declare intermediate signals for referenced outputs
SIGNAL bl_mode_o_xhdl0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL data_mode_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
test_mem_instr_mode <= "0000" when TST_MEM_INSTR_MODE = "BRAM_INSTR_MODE" else
"0001" when (TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") OR
(TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") else
"0010" when TST_MEM_INSTR_MODE = "R_W_INSTR_MODE" else
"0011" when (TST_MEM_INSTR_MODE = "RP_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6") else
"0100" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_INSTR_MODE" AND
FAMILY = "SPARTAN6")else
"0101" when (TST_MEM_INSTR_MODE = "R_RP_W_WP_REF_INSTR_MODE"AND
FAMILY = "SPARTAN6") else
"0010" ;
-- Drive referenced outputs
bl_mode_o <= bl_mode_o_xhdl0;
FIXEDBL <= "000000";
xhdl1 : IF (FAMILY = "SPARTAN6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
INC_COUNTS <= std_logic_vector(to_unsigned(DWIDTH/8,11));
END IF;
END PROCESS;
END GENERATE;
xhdl2 : IF (FAMILY = "VIRTEX6") GENERATE
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (DWIDTH >= 256 AND DWIDTH <= 576) THEN
INC_COUNTS <= "00000100000";
ELSIF ((DWIDTH >= 128) AND (DWIDTH <= 224)) THEN
INC_COUNTS <= "00000010000";
ELSIF ((DWIDTH = 64) OR (DWIDTH = 96)) THEN
INC_COUNTS <= "00000001000";
ELSIF (DWIDTH = 32) THEN
INC_COUNTS <= "00000000100";
END IF;
END IF;
END PROCESS;
END GENERATE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_address <= BEGIN_ADDRESS;
ELSIF (
-- ((mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND ((PORT_MODE = "WR_MODE") OR (PORT_MODE = "BI_MODE")))) OR
(mcb_wr_en_i = '1' AND (current_state = INIT_MEM_WRITE AND (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE"))) OR
(mcb_wr_en_i = '1' AND (current_state = IDLE AND PORT_MODE = "RD_MODE" ))
) THEN
current_address <= current_address + ("000000000000000000000" & INC_COUNTS);
ELSE
current_address <= current_address;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(29 DOWNTO 24) >= end_boundary_addr(29 DOWNTO 24)) THEN
AC3_G_E3 <= '1';
ELSE
AC3_G_E3 <= '0';
END IF;
IF (current_address(23 DOWNTO 16) >= end_boundary_addr(23 DOWNTO 16)) THEN
AC2_G_E2 <= '1';
ELSE
AC2_G_E2 <= '0';
END IF;
IF (current_address(15 DOWNTO 8) >= end_boundary_addr(15 DOWNTO 8)) THEN
AC1_G_E1 <= '1';
ELSE
AC1_G_E1 <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
upper_end_matched <= '0';
ELSIF (mcb_cmd_en_i = '1') THEN
upper_end_matched <= AC3_G_E3 AND AC2_G_E2 AND AC1_G_E1;
END IF;
END IF;
END PROCESS;
FIXED_BL_VALUE <= "0000010" WHEN ((FAMILY = "VIRTEX6") AND ((MEM_BURST_LEN = 8) OR (MEM_BURST_LEN = 0))) ELSE
"0000001" WHEN ((FAMILY = "VIRTEX6") AND (MEM_BURST_LEN = 4)) ELSE
('0' & FIXEDBL);
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
end_boundary_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(END_ADDRESS)) - (DWIDTH / 8) + 1),32));
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (current_address(7 DOWNTO 0) >= end_boundary_addr(7 DOWNTO 0)) THEN
lower_end_matched <= '1';
ELSE
lower_end_matched <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (mcb_cmd_en_i = '1') THEN
mcb_cmd_bl_r <= mcb_cmd_bl_i;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 32)) OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "SPARTAN6" AND (DWIDTH = 64)) OR
(upper_end_matched = '1' AND DWIDTH = 128 AND FAMILY = "SPARTAN6") OR
((upper_end_matched = '1' AND lower_end_matched = '1') AND FAMILY = "VIRTEX6")) THEN
end_addr_reached <= '1';
ELSE
end_addr_reached <= '0';
END IF;
END IF;
END PROCESS;
fixed_addr_o <= "00000000000000000001001000110100";
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
mcb_init_done_reg1 <= mcb_init_done_i;
mcb_init_done_reg <= mcb_init_done_reg1;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
run_traffic_o <= run_traffic;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
current_state <= "00001";
ELSE
current_state <= next_state;
END IF;
END IF;
END PROCESS;
start_addr_o <= BEGIN_ADDRESS;
end_addr_o <= END_ADDRESS;
cmd_seed_o <= CMD_SEED_VALUE;
data_seed_o <= DATA_SEED_VALUE;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
syn1_vio_data_mode_value <= "011";
syn1_vio_addr_mode_value <= "011";
ELSIF (vio_modify_enable = '1') THEN
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1') THEN
data_mode_sel <= DATA_MODE; --"0101" ADDR_DATA_MODE;
addr_mode_sel <= "011";
ELSIF (vio_modify_enable = '1') THEN
data_mode_sel <= '0' & syn1_vio_data_mode_value(2 DOWNTO 0);
addr_mode_sel <= vio_addr_mode_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i = '1') OR (FAMILY = "VIRTEX6")) THEN
fix_bl_value <= FIXED_BL_VALUE(5 DOWNTO 0);
ELSIF (vio_modify_enable = '1') THEN
fix_bl_value <= vio_fixed_bl_value;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i = '1' OR (FAMILY = "VIRTEX6")) THEN
IF (FAMILY = "VIRTEX6") THEN
bl_mode_sel <= FIXED_BL_MODE;
ELSE
bl_mode_sel <= PRBS_BL_MODE;
END IF;
ELSIF (vio_modify_enable = '1') THEN
bl_mode_sel <= vio_bl_mode_value;
END IF;
END IF;
END PROCESS;
data_mode_o <= data_mode_reg;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
data_mode_reg <= data_mode_sel;
addr_mode_o <= addr_mode;
IF (syn1_vio_addr_mode_value = 0 AND vio_modify_enable = '1') THEN
bram_mode_enable <= '1';
ELSE
bram_mode_enable <= '0';
END IF;
END IF;
END PROCESS;
PROCESS (FIXED_BL_VALUE,fix_bl_value,bram_mode_enable,test_mem_instr_mode, current_state, mcb_init_done_reg, end_addr_reached, cmp_error, bl_mode_sel, addr_mode_sel, data_mode_reg,bl_mode_o_xhdl0)
BEGIN
load_seed_o <= '0';
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
addr_mode <= (others => '0');
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
instr_mode_o <= (others => '0');
ELSE
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
IF (CMD_PATTERN = "CGEN_BRAM" or bram_mode_enable = '1') THEN
bl_mode_o_xhdl0 <= (others => '0');
ELSE
bl_mode_o_xhdl0 <= FIXED_BL_MODE;
END IF;
-- data_mode1 <= WALKING1_DATA_MODE;
IF (FAMILY = "VIRTEX6") THEN
fixed_bl_o <= FIXED_BL_VALUE(5 downto 0); --"000010"; --2
-- PRBS mode
else if (data_mode_reg(2 downto 0) = "111" and FAMILY = "SPARTAN6") then
fixed_bl_o <= "000000";-- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
mode_load_o <= '0';
run_traffic <= '0';
next_state <= IDLE;
IF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
CASE current_state IS
WHEN IDLE =>
IF (mcb_init_done_reg = '1') THEN
IF (PORT_MODE = "WR_MODE" OR PORT_MODE = "BI_MODE") THEN
next_state <= INIT_MEM_WRITE;
mode_load_o <= '1';
run_traffic <= '0';
load_seed_o <= '1';
ELSIF (PORT_MODE = "RD_MODE" AND end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
run_traffic <= '1';
load_seed_o <= '1';
END IF;
ELSE
next_state <= IDLE;
run_traffic <= '0';
load_seed_o <= '0';
END IF;
WHEN INIT_MEM_WRITE =>
IF (end_addr_reached = '1' AND EYE_TEST = "FALSE") THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
run_traffic <= '1';
ELSE
next_state <= INIT_MEM_WRITE;
run_traffic <= '1';
mode_load_o <= '0';
load_seed_o <= '0';
IF (EYE_TEST = "TRUE") THEN
addr_mode <= FIXED_ADDR;
ELSIF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
addr_mode <= "000";
ELSE
addr_mode <= SEQUENTIAL_ADDR;
END IF;
END IF;
WHEN INIT_MEM_READ =>
IF (end_addr_reached = '1') THEN
next_state <= TEST_MEM;
mode_load_o <= '1';
load_seed_o <= '1';
ELSE
next_state <= INIT_MEM_READ;
run_traffic <= '0';
mode_load_o <= '0';
load_seed_o <= '0';
END IF;
WHEN TEST_MEM =>
IF (cmp_error = '1') THEN
next_state <= CMP_ERROR1;
ELSE
next_state <= TEST_MEM;
END IF;
run_traffic <= '1';
IF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_W_MODE") THEN
fixed_instr_o <= WR_INSTR;
ELSIF (PORT_MODE = "BI_MODE" AND TST_MEM_INSTR_MODE = "FIXED_INSTR_R_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "RD_MODE") THEN
fixed_instr_o <= RD_INSTR;
ELSIF (PORT_MODE = "WR_MODE") THEN
fixed_instr_o <= WR_INSTR;
END IF;
if (FAMILY = "VIRTEX6") then
fixed_bl_o <= fix_bl_value; --"000010"; 2
else if ((data_mode_reg = "0111") and (FAMILY = "SPARTAN6")) then
fixed_bl_o <= "000000"; -- 64 Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o <= fix_bl_value;
end if;
end if;
bl_mode_o_xhdl0 <= bl_mode_sel;
IF (bl_mode_o_xhdl0 = PRBS_BL_MODE) THEN
addr_mode <= PRBS_ADDR;
ELSE
addr_mode <= addr_mode_sel;
END IF;
IF (PORT_MODE = "BI_MODE") THEN
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_RP_W_WP_REF_INSTR_MODE;--FIXED_INSTR_MODE;--R_W_INSTR_MODE;--R_RP_W_WP_INSTR_MODE;--R_W_INSTR_MODE;
--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
ELSIF (PORT_MODE = "RD_MODE" OR PORT_MODE = "WR_MODE") THEN
instr_mode_o <= FIXED_INSTR_MODE;
END IF;
WHEN CMP_ERROR1 =>
next_state <= CMP_ERROR1;
bl_mode_o_xhdl0 <= bl_mode_sel;
fixed_instr_o <= RD_INSTR;
addr_mode <= SEQUENTIAL_ADDR;
IF (CMD_PATTERN = "CGEN_BRAM" OR bram_mode_enable = '1') THEN
instr_mode_o <= BRAM_INSTR_MODE;
ELSE
instr_mode_o <= test_mem_instr_mode;
--R_W_INSTR_MODE;--R_W_INSTR_MODE; --FIXED_INSTR_MODE;--
END IF;
run_traffic <= '1';
WHEN OTHERS =>
next_state <= IDLE;
END CASE;
END PROCESS;
END trans;

539
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_flow_control.vhd vendored Executable file
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@@ -0,0 +1,539 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: mcb_flow_control.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module is the main flow control between cmd_gen.v,
-- write_data_path and read_data_path modules.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
ENTITY mcb_flow_control IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_i : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mcb_cmd_full : IN STD_LOGIC;
cmd_o : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_o : OUT STD_LOGIC;
last_word_wr_i : IN STD_LOGIC;
wdp_rdy_i : IN STD_LOGIC;
wdp_valid_o : OUT STD_LOGIC;
wdp_validB_o : OUT STD_LOGIC;
wdp_validC_o : OUT STD_LOGIC;
wr_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
last_word_rd_i : IN STD_LOGIC;
rdp_rdy_i : IN STD_LOGIC;
rdp_valid_o : OUT STD_LOGIC;
rd_addr_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rd_bl_o : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END mcb_flow_control;
ARCHITECTURE trans OF mcb_flow_control IS
constant READY : std_logic_vector(4 downto 0) := "00001";
constant READ : std_logic_vector(4 downto 0) := "00010";
constant WRITE : std_logic_vector(4 downto 0) := "00100";
constant CMD_WAIT : std_logic_vector(4 downto 0) := "01000";
constant REFRESH_ST : std_logic_vector(4 downto 0) := "10000";
constant RD : std_logic_vector(2 downto 0) := "001";
constant RDP : std_logic_vector(2 downto 0) := "011";
constant WR : std_logic_vector(2 downto 0) := "000";
constant WRP : std_logic_vector(2 downto 0) := "010";
constant REFRESH : std_logic_vector(2 downto 0) := "100";
constant NOP : std_logic_vector(2 downto 0) := "101";
SIGNAL cmd_fifo_rdy : STD_LOGIC;
SIGNAL cmd_rd : STD_LOGIC;
SIGNAL cmd_wr : STD_LOGIC;
SIGNAL cmd_others : STD_LOGIC;
SIGNAL push_cmd : STD_LOGIC;
SIGNAL xfer_cmd : STD_LOGIC;
SIGNAL rd_vld : STD_LOGIC;
SIGNAL wr_vld : STD_LOGIC;
SIGNAL cmd_rdy : STD_LOGIC;
SIGNAL cmd_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL addr_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bl_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL rdp_valid : STD_LOGIC;
SIGNAL wdp_valid : STD_LOGIC;
SIGNAL wdp_validB : STD_LOGIC;
SIGNAL wdp_validC : STD_LOGIC;
SIGNAL current_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL next_state : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL tstpointA : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL push_cmd_r : STD_LOGIC;
SIGNAL wait_done : STD_LOGIC;
SIGNAL cmd_en_r1 : STD_LOGIC;
SIGNAL wr_in_progress : STD_LOGIC;
SIGNAL tst_cmd_rdy_o : STD_LOGIC;
SIGNAL cmd_wr_pending_r1 : STD_LOGIC;
SIGNAL cmd_rd_pending_r1 : STD_LOGIC;
-- Declare intermediate signals for referenced outputs
SIGNAL cmd_rdy_o_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
cmd_en_o <= cmd_en_r1;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
cmd_rdy_o_xhdl0 <= cmd_rdy;
tst_cmd_rdy_o <= cmd_rdy;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
cmd_en_r1 <= '0' ;
ELSIF (xfer_cmd = '1') THEN
cmd_en_r1 <= '1' ;
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_en_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
cmd_fifo_rdy <= '1';
ELSIF (xfer_cmd = '1') THEN
cmd_fifo_rdy <= '0';
ELSIF ((NOT(mcb_cmd_full)) = '1') THEN
cmd_fifo_rdy <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(9)) = '1') THEN
addr_o <= (others => '0');
cmd_o <= (others => '0');
bl_o <= (others => '0');
ELSIF (xfer_cmd = '1') THEN
addr_o <= addr_reg;
IF (FAMILY = "SPARTAN6") THEN
cmd_o <= cmd_reg;
ELSE
cmd_o <= ("00" & cmd_reg(0));
END IF;
bl_o <= bl_reg;
END IF;
END IF;
END PROCESS;
wr_addr_o <= addr_i;
rd_addr_o <= addr_i;
rd_bl_o <= bl_i;
wr_bl_o <= bl_i;
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
rdp_valid_o <= rdp_valid;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((rst_i(8)) = '1') THEN
wait_done <= '1' ;
ELSIF (push_cmd_r = '1') THEN
wait_done <= '1' ;
ELSIF ((cmd_rdy_o_xhdl0 AND cmd_valid_i) = '1' AND FAMILY = "SPARTAN6") THEN
wait_done <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
push_cmd_r <= push_cmd ;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (push_cmd = '1') THEN
cmd_reg <= cmd_i ;
addr_reg <= addr_i ;
bl_reg <= bl_i - "000001" ;
END IF;
END IF;
END PROCESS;
cmd_wr <= '1' WHEN (((cmd_i = WR) OR (cmd_i = WRP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_rd <= '1' WHEN (((cmd_i = RD) OR (cmd_i = RDP)) AND (cmd_valid_i = '1')) ELSE
'0';
cmd_others <= '1' WHEN ((cmd_i(2) = '1') AND (cmd_valid_i = '1') AND (FAMILY = "SPARTAN6")) ELSE
'0';
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
cmd_wr_pending_r1 <= '0' ;
ELSIF (last_word_wr_i = '1') THEN
cmd_wr_pending_r1 <= '1' ;
ELSIF (push_cmd = '1') THEN
cmd_wr_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF ((cmd_rd AND push_cmd) = '1') THEN
cmd_rd_pending_r1 <= '1' ;
ELSIF (xfer_cmd = '1') THEN
cmd_rd_pending_r1 <= '0' ;
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
wr_in_progress <= '0';
ELSIF (last_word_wr_i = '1') THEN
wr_in_progress <= '0';
ELSIF (current_state = WRITE) THEN
wr_in_progress <= '1';
END IF;
END IF;
END PROCESS;
PROCESS (clk_i)
BEGIN
IF (clk_i'EVENT AND clk_i = '1') THEN
IF (rst_i(0)= '1') THEN
current_state <= "00001" ;
ELSE
current_state <= next_state ;
END IF;
END IF;
END PROCESS;
PROCESS (current_state, rdp_rdy_i, cmd_rd, cmd_fifo_rdy, wdp_rdy_i, cmd_wr, last_word_rd_i, cmd_others, last_word_wr_i, cmd_valid_i, wait_done, wr_in_progress, cmd_wr_pending_r1)
BEGIN
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
cmd_rdy <= '0';
next_state <= current_state;
CASE current_state IS
WHEN READY =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '0';
rdp_valid <= '1';
ELSIF ((wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '0';
ELSE
next_state <= READY;
push_cmd <= '0';
END IF;
IF (cmd_fifo_rdy = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN REFRESH_ST =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSIF ((cmd_fifo_rdy and cmd_others) = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSIF ((not(cmd_fifo_rdy)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((cmd_fifo_rdy AND ((rdp_rdy_i AND cmd_rd) OR (wdp_rdy_i AND cmd_wr) OR (cmd_others))) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN READ =>
IF ((rdp_rdy_i AND cmd_rd AND cmd_fifo_rdy) = '1') THEN
next_state <= READ;
push_cmd <= '1';
rdp_valid <= '1';
wdp_valid <= '0';
xfer_cmd <= '1';
tstpointA <= "0101";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND wdp_rdy_i) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
tstpointA <= "0110";
ELSIF ((NOT(rdp_rdy_i)) = '1') THEN
next_state <= READ;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0111";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((last_word_rd_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
tstpointA <= "1000";
ELSIF ((NOT(cmd_fifo_rdy) OR NOT(wdp_rdy_i)) = '1') THEN
next_state <= CMD_WAIT;
tstpointA <= "1001";
ELSE
next_state <= READ;
END IF;
IF ((((rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i) OR cmd_others) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done; --'1';
ELSE
cmd_rdy <= '0';
END IF;
WHEN WRITE =>
IF ((cmd_fifo_rdy AND cmd_rd AND rdp_rdy_i AND last_word_wr_i) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
rdp_valid <= '1';
tstpointA <= "0000";
ELSIF ((NOT(wdp_rdy_i) OR (wdp_rdy_i AND cmd_wr AND cmd_fifo_rdy AND last_word_wr_i)) = '1') THEN
next_state <= WRITE;
tstpointA <= "0001";
IF ((cmd_wr AND last_word_wr_i) = '1') THEN
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
ELSE
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
END IF;
IF (last_word_wr_i = '1') THEN
push_cmd <= '1';
xfer_cmd <= '1';
ELSE
push_cmd <= '0';
xfer_cmd <= '0';
END IF;
ELSIF ((last_word_wr_i AND cmd_others AND cmd_fifo_rdy) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "0010";
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
rdp_valid <= '0';
ELSIF ((((NOT(cmd_fifo_rdy)) AND last_word_wr_i) OR (NOT(rdp_rdy_i)) OR (NOT(cmd_valid_i) AND wait_done)) = '1') THEN
next_state <= CMD_WAIT;
push_cmd <= '0';
xfer_cmd <= '0';
tstpointA <= "0011";
ELSE
next_state <= WRITE;
tstpointA <= "0100";
END IF;
IF ((last_word_wr_i AND (cmd_others OR (rdp_rdy_i AND cmd_rd) OR (cmd_wr AND wdp_rdy_i)) AND cmd_fifo_rdy) = '1') THEN
cmd_rdy <= wait_done;
ELSE
cmd_rdy <= '0';
END IF;
WHEN CMD_WAIT =>
IF ((NOT(cmd_fifo_rdy) OR wr_in_progress) = '1') THEN
next_state <= CMD_WAIT;
cmd_rdy <= '0';
tstpointA <= "1010";
ELSIF ((cmd_fifo_rdy AND rdp_rdy_i AND cmd_rd) = '1') THEN
next_state <= READ;
push_cmd <= '1';
xfer_cmd <= '1';
cmd_rdy <= '1';
rdp_valid <= '1';
tstpointA <= "1011";
ELSIF ((cmd_fifo_rdy AND cmd_wr AND (wait_done OR cmd_wr_pending_r1)) = '1') THEN
next_state <= WRITE;
push_cmd <= '1';
xfer_cmd <= '1';
wdp_valid <= '1';
wdp_validB <= '1';
wdp_validC <= '1';
cmd_rdy <= '1';
tstpointA <= "1100";
ELSIF ((cmd_fifo_rdy AND cmd_others) = '1') THEN
next_state <= REFRESH_ST;
push_cmd <= '1';
xfer_cmd <= '1';
tstpointA <= "1101";
cmd_rdy <= '1';
ELSE
next_state <= CMD_WAIT;
tstpointA <= "1110";
IF (((wdp_rdy_i AND rdp_rdy_i)) = '1') THEN
cmd_rdy <= '1';
ELSE
cmd_rdy <= '0';
END IF;
END IF;
WHEN OTHERS =>
push_cmd <= '0';
xfer_cmd <= '0';
wdp_valid <= '0';
wdp_validB <= '0';
wdp_validC <= '0';
next_state <= READY;
END CASE;
END PROCESS;
END trans;

1001
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/mcb_traffic_gen.vhd vendored Executable file
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File diff suppressed because it is too large Load Diff

434
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/rd_data_gen.vhd vendored Executable file
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@@ -0,0 +1,434 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: rd_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module has all the timing control for generating "compare data"
-- to compare the read data from memory.
-- Reference:
-- Revision History: 2010/01/09 parameter MEM_BURST_LEN is missing in v6_data_gen instance module.
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity rd_data_gen is
generic (
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
rd_mdata_en : in std_logic;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen in sp6
-- connect from mcb_rd_empty when used as rd_data_gen in sp6
-- connect from rd_data_valid in v6
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity rd_data_gen;
ARCHITECTURE trans OF rd_data_gen IS
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
MEM_BURST_LEN : integer := 8;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_ALL";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
SIGNAL prbs_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL cmd_start : STD_LOGIC;
SIGNAL adata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL hdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL ndata : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL w1data : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL v6_w1data : STD_LOGIC_VECTOR(NUM_DQ_PINS * 4 - 1 DOWNTO 0);
signal w0data : std_logic_vector(31 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal data_rdy_r1 : std_logic;
signal data_rdy_r2 : std_logic;
signal next_count_is_one : std_logic;
signal cmd_valid_r1 : std_logic;
signal w3data : std_logic_vector(31 downto 0);
signal data_port_fifo_rdy : std_logic;
--assign cmd_start = cmd_valid_i & cmd_rdy ;
signal user_bl_cnt_is_1 : std_logic;
signal cmd_start_b : std_logic;
-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
-- need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
-- counter to count user burst length
signal u_bcount_2 : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_port_fifo_rdy <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_rdy_r1 <= data_rdy_i;
data_rdy_r2 <= data_rdy_r1;
cmd_valid_r1 <= cmd_valid_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (user_burst_cnt = "0000010" and data_rdy_i = '1') then
next_count_is_one <= '1';
else
next_count_is_one <= '0';
end if;
end if;
end process;
user_bl_cnt_is_1_o <= user_bl_cnt_is_1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "SPARTAN6") or
(user_burst_cnt = "0000010" and data_port_fifo_rdy = '1' and FAMILY = "VIRTEX6") ) then
user_bl_cnt_is_1 <= '1';
else
user_bl_cnt_is_1 <= '0';
end if;
end if;
end process;
process (cmd_valid_i, cmd_valid_r1, cmd_rdy, user_bl_cnt_is_1, rd_mdata_en)
begin
if (FAMILY = "SPARTAN6") then
cmd_start <= cmd_valid_i and cmd_rdy;
cmd_start_b <= cmd_valid_i and cmd_rdy;
else
if (MEM_BURST_LEN = 4) then
cmd_start <= rd_mdata_en;
else
cmd_start <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
cmd_start_b <= (not(cmd_valid_r1) and cmd_valid_i) or user_bl_cnt_is_1;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000";
elsif (cmd_start = '1') then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (data_port_fifo_rdy = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001";
else
user_burst_cnt <= "0000000";
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and data_rdy_i = '1') or (cmd_start = '1' and bl_i = "000001")) then
u_bcount_2 <= '1';
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0';
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and data_rdy_i;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
--data_valid_o logic
cmd_rdy_o <= cmd_rdy;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1';
elsif (cmd_start = '1') then
cmd_rdy <= '0';
elsif (data_port_fifo_rdy = '1' and user_burst_cnt = "0000001") then
cmd_rdy <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
data_valid <= '0';
elsif (user_burst_cnt = "0000001" and data_port_fifo_rdy = '1') then
data_valid <= '0';
elsif ((user_burst_cnt >= "0000001") or cmd_start = '1') then
data_valid <= '1';
end if;
end if;
end process;
process (data_valid, data_port_fifo_rdy)
begin
if (FAMILY = "SPARTAN6") then
data_valid_o <= data_valid;
else
data_valid_o <= data_port_fifo_rdy;
end if;
end process;
xhdl2 : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_start,
cmd_startC => cmd_start,
cmd_startD => cmd_start,
cmd_startE => cmd_start,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => data_port_fifo_rdy,
data_o => data_o
);
end generate;
xhdl3 : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_start,
cmd_startC => cmd_start,
cmd_startD => cmd_start,
cmd_startE => cmd_start,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --(m_addr_i ),
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => data_port_fifo_rdy,
data_o => data_o
);
end generate;
end architecture trans;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_data_path.vhd vendored Executable file
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@@ -0,0 +1,638 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/read_posted_fifo.vhd vendored Executable file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_posted_fifo.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module instantiated by read_data_path module and sits between
-- mcb_flow_control module and read_data_gen module to buffer up the
-- commands that has sent to memory controller.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity read_posted_fifo is
generic (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
data_valid_i : in std_logic;
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1 : in std_logic;
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
gen_rdy_i : in std_logic;
gen_valid_o : out std_logic;
gen_addr_o : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
gen_bl_o : out std_logic_vector(BL_WIDTH - 1 downto 0);
rd_buff_avail_o : out std_logic_vector(6 downto 0);
rd_mdata_fifo_empty : in std_logic;
rd_mdata_en : out std_logic
);
end entity read_posted_fifo;
architecture trans of read_posted_fifo is
component afifo is
generic (
DSIZE : integer := 32;
FIFO_DEPTH : integer := 16;
ASIZE : integer := 4;
SYNC : integer := 1
);
port (
wr_clk : in std_logic;
rst : in std_logic;
wr_en : in std_logic;
wr_data : in std_logic_vector(DSIZE - 1 downto 0);
rd_en : in std_logic;
rd_clk : in std_logic;
rd_data : out std_logic_vector(DSIZE - 1 downto 0);
full : out std_logic;
empty : out std_logic;
almost_full : out std_logic
);
end component;
signal full : std_logic;
signal empty : std_logic;
signal wr_en : std_logic;
signal rd_en : std_logic;
signal data_valid_r : std_logic;
signal user_bl_cnt_not_1 : std_logic;
signal buf_avail_r : std_logic_vector(6 downto 0);
signal rd_data_received_counts : std_logic_vector(6 downto 0);
signal rd_data_counts_asked : std_logic_vector(6 downto 0);
signal dfifo_has_enough_room : std_logic;
signal wait_cnt : std_logic_vector(1 downto 0);
signal wait_done : std_logic;
signal dfifo_has_enough_room_d1 : std_logic;
signal empty_r : std_logic;
signal rd_first_data : std_logic;
-- current count is 1 and data_is_valie, then next cycle is not 1
-- calculate how many buf still available
-- assign buf_avail = 64 - (rd_data_counts_asked - rd_data_received_counts);
-- signal tmp_buf_avil : std_logic_vector(5 downto 0);
-- X-HDL generated signals
signal xhdl3 : std_logic;
signal xhdl4 : std_logic;
signal xhdl5 : std_logic_vector(37 downto 0);
signal xhdl6 : std_logic_vector(37 downto 0);
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal gen_addr_o_xhdl1 : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal gen_bl_o_xhdl2 : std_logic_vector(BL_WIDTH - 1 downto 0);
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
-- gen_addr_o <= gen_addr_o_xhdl1;
-- gen_bl_o <= gen_bl_o_xhdl2;
gen_bl_o <= xhdl6(BL_WIDTH+ADDR_WIDTH-1 downto ADDR_WIDTH);
gen_addr_o <= xhdl6(ADDR_WIDTH-1 downto 0);
rd_mdata_en <= rd_en;
rd_buff_avail_o <= buf_avail_r;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_rdy_o_xhdl0 <= not(full) and dfifo_has_enough_room and wait_done;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_cnt <= "00";
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_cnt <= "10";
elsif (wait_cnt > "00") then
wait_cnt <= wait_cnt - "01";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
wait_done <= '1';
elsif ((cmd_rdy_o_xhdl0 and cmd_valid_i) = '1') then
wait_done <= '0';
elsif (wait_cnt = "00") then
wait_done <= '1';
else
wait_done <= '0';
end if;
end if;
end process;
xhdl3 <= '1' when (buf_avail_r >= "0111110") else
'0';
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
dfifo_has_enough_room <= xhdl3;
dfifo_has_enough_room_d1 <= dfifo_has_enough_room;
end if;
end process;
wr_en <= cmd_valid_i and not(full) and dfifo_has_enough_room_d1 and wait_done;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_valid_r <= data_valid_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((data_valid_i and user_bl_cnt_is_1) = '1') then
user_bl_cnt_not_1 <= '1';
else
user_bl_cnt_not_1 <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_counts_asked <= (others => '0');
elsif (cmd_en_i = '1' and cmd_sent(0) = '1') then
rd_data_counts_asked <= rd_data_counts_asked + (bl_sent + "0000001" );
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_data_received_counts <= "0000000";
elsif (data_valid_i = '1') then
rd_data_received_counts <= rd_data_received_counts + "0000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
buf_avail_r <= "1000000" - (rd_data_counts_asked - rd_data_received_counts);
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
empty_r <= empty;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
rd_first_data <= '0';
elsif ( empty = '0' AND empty_r = '1') then
rd_first_data <= '1';
end if;
end if;
end process;
process (gen_rdy_i, empty,empty_r, data_valid_i, data_valid_r, user_bl_cnt_not_1,rd_mdata_fifo_empty,rd_first_data)
begin
if (FAMILY = "SPARTAN6") then
rd_en <= gen_rdy_i and not(empty);
else
IF (MEM_BURST_LEN = 4) then
rd_en <= (not(empty) and empty_r and not(rd_first_data)) or (not(rd_mdata_fifo_empty) and not(empty)) or
(user_bl_cnt_not_1 and data_valid_i);
ELSE
rd_en <= (data_valid_i and not(data_valid_r)) or (user_bl_cnt_not_1 and data_valid_i);
END IF;
end if;
end process;
gen_valid_o <= not(empty);
-- set the SYNC to 1 because rd_clk = wr_clk to reduce latency
-- xhdl4 <= to_integer(to_stdlogic(BL_WIDTH) + to_stdlogic(ADDR_WIDTH));
xhdl5 <= (bl_i & addr_i);
-- (gen_bl_o_xhdl2, gen_addr_o_xhdl1) <= xhdl6;
rd_fifo : afifo
GENERIC MAP (
DSIZE => (BL_WIDTH + ADDR_WIDTH),--xhdl4,
FIFO_DEPTH => 16,
ASIZE => 4,
SYNC => 1
)
port map (
wr_clk => clk_i,
rst => rst_i,
wr_en => wr_en,
wr_data => xhdl5,
rd_en => rd_en,
rd_clk => clk_i,
rd_data => xhdl6,
full => full,
empty => empty,
almost_full => open
);
end architecture trans;

793
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/sp6_data_gen.vhd vendored Executable file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: sp6_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:40 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module generates different data pattern as described in
-- parameter DATA_PATTERN and is set up for Spartan 6 family.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity sp6_data_gen is
generic (
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic; --
rst_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
data_rdy_i : in std_logic;
cmd_startA : in std_logic;
cmd_startB : in std_logic;
cmd_startC : in std_logic;
cmd_startD : in std_logic;
cmd_startE : in std_logic;
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
user_burst_cnt : in std_logic_vector(6 downto 0); -- generated burst length for control the burst data
fifo_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_o : out std_logic_vector(DWIDTH - 1 downto 0) -- generated data pattern
);
end entity sp6_data_gen;
architecture trans of sp6_data_gen is
COMPONENT data_prbs_gen IS
GENERIC (
EYE_TEST : STRING := "FALSE";
PRBS_WIDTH : INTEGER := 32;
SEED_WIDTH : INTEGER := 32
);
PORT (
clk_i : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
prbs_seed_init : IN STD_LOGIC;
prbs_seed_i : IN STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0);
prbs_o : OUT STD_LOGIC_VECTOR(PRBS_WIDTH - 1 DOWNTO 0)
);
END COMPONENT;
--
signal prbs_data : std_logic_vector(31 downto 0);
signal adata : std_logic_vector(31 downto 0);
signal hdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata : std_logic_vector(DWIDTH - 1 downto 0);
signal w1data : std_logic_vector(DWIDTH - 1 downto 0);
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal walk_cnt : std_logic_vector(2 downto 0);
signal user_address : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal i : integer;
signal j : integer;
signal user_bl : std_logic_vector(BL_WIDTH - 1 downto 0);
signal BLANK : std_logic_vector(7 downto 0);
signal SHIFT_0 : std_logic_vector(7 downto 0);
signal SHIFT_1 : std_logic_vector(7 downto 0);
signal SHIFT_2 : std_logic_vector(7 downto 0);
signal SHIFT_3 : std_logic_vector(7 downto 0);
signal SHIFT_4 : std_logic_vector(7 downto 0);
signal SHIFT_5 : std_logic_vector(7 downto 0);
signal SHIFT_6 : std_logic_vector(7 downto 0);
signal SHIFT_7 : std_logic_vector(7 downto 0);
signal SHIFTB_0 : std_logic_vector(31 downto 0);
signal SHIFTB_1 : std_logic_vector(31 downto 0);
signal SHIFTB_2 : std_logic_vector(31 downto 0);
signal SHIFTB_3 : std_logic_vector(31 downto 0);
signal SHIFTB_4 : std_logic_vector(31 downto 0);
signal SHIFTB_5 : std_logic_vector(31 downto 0);
signal SHIFTB_6 : std_logic_vector(31 downto 0);
signal SHIFTB_7 : std_logic_vector(31 downto 0);
signal TSTB : std_logic_vector(3 downto 0);
--*********************************************************************************************
-- 4'b0000: data = 32'b0; //bram
-- 4'b0001: data = 32'b0; // fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
--bram
-- fixed
-- address as data
-- DGEN_HAMMER
-- DGEN_NEIGHBOUR
-- DGEN_WALKING1
-- DGEN_WALKING0
-- WALKING ONES:
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
-- WALKING ONE
-- NEIGHBOR ONE
-- WALKING ZERO
signal tmpdata : std_logic_vector(DWIDTH - 1 downto 0);
signal ndata_rising : std_logic;
signal shift_en : std_logic;
signal data_clk_en : std_logic;
SIGNAL ZEROS : STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0) ;--:= (others => '0');
begin
ZEROS <= (others => '0');
data_o <= data;
xhdl0 : if (DWIDTH = 32) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0001" =>
data <= fixed_data_i;
when "0010" =>
data <= adata;
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
data <= prbs_data;
WHEN OTHERS =>
data <= (others => '0');
END CASE;
END PROCESS;
end generate;
xhdl1 : if (DWIDTH = 64) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata)(31 downto 0);
data <= (adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data);
when others =>
data <= (others => '0');
end case;
end process;
end generate;
xhdl2 : if (DWIDTH = 128) generate
process (adata, hdata, ndata, w1data, prbs_data, data_mode_i,fixed_data_i)
begin
case data_mode_i is
when "0000" =>
data <= (others => '0');
when "0001" =>
data <= fixed_data_i;
when "0010" =>
-- data <= (adata & adata & adata & adata)(31 downto 0);
data <= (adata & adata & adata & adata);
when "0011" =>
data <= hdata;
when "0100" =>
data <= ndata;
when "0101" =>
data <= w1data;
when "0110" =>
data <= w1data;
when "0111" =>
-- data <= (prbs_data & prbs_data & prbs_data & prbs_data)(31 downto 0);
data <= (prbs_data & prbs_data & prbs_data & prbs_data);
when others =>
data <= (others => '0');--"00000000000000000000000000000000";
end case;
end process;
end generate;
xhdl3 : if ((DWIDTH = 64) or (DWIDTH = 128)) generate
process (data_mode_i)
begin
if (data_mode_i = "0101" or data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0100") then
BLANK <= "00000000";
SHIFT_0 <= "00000001";
SHIFT_1 <= "00000010";
SHIFT_2 <= "00000100";
SHIFT_3 <= "00001000";
SHIFT_4 <= "00010000";
SHIFT_5 <= "00100000";
SHIFT_6 <= "01000000";
SHIFT_7 <= "10000000";
elsif (data_mode_i = "0110") then
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
else
BLANK <= "11111111";
SHIFT_0 <= "11111110";
SHIFT_1 <= "11111101";
SHIFT_2 <= "11111011";
SHIFT_3 <= "11110111";
SHIFT_4 <= "11101111";
SHIFT_5 <= "11011111";
SHIFT_6 <= "10111111";
SHIFT_7 <= "01111111";
end if;
end process;
end generate;
process (data_mode_i)
begin
if (data_mode_i = "0101") then
SHIFTB_0 <= "00000000000000100000000000000001";
SHIFTB_1 <= "00000000000010000000000000000100";
SHIFTB_2 <= "00000000001000000000000000010000";
SHIFTB_3 <= "00000000100000000000000001000000";
SHIFTB_4 <= "00000010000000000000000100000000";
SHIFTB_5 <= "00001000000000000000010000000000";
SHIFTB_6 <= "00100000000000000001000000000000";
SHIFTB_7 <= "10000000000000000100000000000000";
elsif (data_mode_i = "0100") then
SHIFTB_0 <= "00000000000000000000000000000001";
SHIFTB_1 <= "00000000000000000000000000000010";
SHIFTB_2 <= "00000000000000000000000000000100";
SHIFTB_3 <= "00000000000000000000000000001000";
SHIFTB_4 <= "00000000000000000000000000010000";
SHIFTB_5 <= "00000000000000000000000000100000";
SHIFTB_6 <= "00000000000000000000000001000000";
SHIFTB_7 <= "00000000000000000000000010000000";
else
SHIFTB_0 <= "11111111111111011111111111111110";
SHIFTB_1 <= "11111111111101111111111111111011";
SHIFTB_2 <= "11111111110111111111111111101111";
SHIFTB_3 <= "11111111011111111111111110111111";
SHIFTB_4 <= "11111101111111111111111011111111";
SHIFTB_5 <= "11110111111111111111101111111111";
SHIFTB_6 <= "11011111111111111110111111111111";
SHIFTB_7 <= "01111111111111111011111111111111";
end if;
end process;
xhdl4 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
ndata_rising <= '1';
shift_en <= '0';
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 2) is
when "000" =>
w1data <= SHIFTB_0;
when "001" =>
w1data <= SHIFTB_1;
when "010" =>
w1data <= SHIFTB_2;
when "011" =>
w1data <= SHIFTB_3;
when "100" =>
w1data <= SHIFTB_4;
when "101" =>
w1data <= SHIFTB_5;
when "110" =>
w1data <= SHIFTB_6;
when "111" =>
w1data <= SHIFTB_7;
when others =>
w1data <= SHIFTB_0;
end case;
ndata_rising <= '0'; --(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
elsif (data_mode_i = "0100") then
w1data <= ("0000000000000000" & w1data(14 downto 0) & w1data(15));
else
w1data <= (w1data(29 downto 16) & w1data(31 downto 30) & w1data(13 downto 0) & w1data(15 downto 14)); --(DQ_PINS == 16
end if;
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
case addr_i(2) is
when '0' =>
w1data <= SHIFTB_0;
when '1' =>
w1data <= SHIFTB_1;
when others =>
w1data <= SHIFTB_0;
end case;
else
-- (cmd_startC)
-- Shifting
-- need neigbour pattern ********************
w1data <= (w1data(27 downto 24) & w1data(31 downto 28) & w1data(19 downto 16) & w1data(23 downto 20) & w1data(11 downto 8) & w1data(15 downto 12) & w1data(3 downto 0) & w1data(7 downto 4)); --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
-- need neigbour pattern ********************
if (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001"; -- (NUM_DQ_PINS_4
end if;
end if;
end if;
end if;
end process;
-- <outdent> -- DWIDTH == 32
end generate;
xhdl5 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4 downto 3) is
-- 7:0
when "00" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
when "01" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
when "10" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
when "11" =>
w1data(2 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= (ZEROS(DWIDTH-1 downto 8) & BLANK);
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(45 downto 32) & w1data(47 downto 46));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(13 downto 0) & w1data(15 downto 14));
else
-- w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) & w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) & w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) & w1data(1 * DWIDTH / 4 - 5 to 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4))(31 downto 0);
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 5 downto 4 * DWIDTH / 4 - 16) &
w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 4) &
w1data(3 * DWIDTH / 4 - 5 downto 3 * DWIDTH / 4 - 16) &
w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 4) &
w1data(2 * DWIDTH / 4 - 5 downto 2 * DWIDTH / 4 - 16) &
w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 4) &
w1data(1 * DWIDTH / 4 - 5 downto 1 * DWIDTH / 4 - 16) &
w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 4));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
case addr_i(3) is
when '0' =>
w1data <= (BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
when '1' =>
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4);
--15:8
when others =>
w1data <= (others => '0');--"00000000000000000000000000000000";
end case;
else
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
w1data <= ("10000000010000000010000000010000" & "00001000000001000000001000000001"); --**** checked
end if;
-- Shifting
elsif (data_mode_i = "0100") then
w1data(63 downto 56) <= "00000000";
w1data(55 downto 48) <= (w1data(51 downto 48) & w1data(55 downto 52));
w1data(47 downto 40) <= "00000000";
w1data(39 downto 32) <= (w1data(35 downto 32) & w1data(39 downto 36));
w1data(31 downto 24) <= "00000000";
w1data(23 downto 16) <= (w1data(19 downto 16) & w1data(23 downto 20));
w1data(15 downto 8) <= "00000000";
w1data(7 downto 0) <= (w1data(3 downto 0) & w1data(7 downto 4));
else
w1data <= w1data; --(NUM_DQ_PINS == 8)
end if;
elsif (NUM_DQ_PINS = 4) then -- NUM_DQ_PINS == 4
if (data_mode_i = "0100") then
w1data <= "0000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "1000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end if;
end process;
end generate;
xhdl6 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_WALKING0" or DATA_PATTERN = "DGEN_WALKING1" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
w1data <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= "0000000") or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
if (cmd_startC = '1') then
case addr_i(4) is
-- 32
when '0' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_0(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_1(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_2(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_3(31 downto 0);
-- 32
when '1' =>
w1data(1 * DWIDTH / 4 - 1 downto 0 * DWIDTH / 4) <= SHIFTB_4(31 downto 0);
w1data(2 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4) <= SHIFTB_5(31 downto 0);
w1data(3 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4) <= SHIFTB_6(31 downto 0);
w1data(4 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4) <= SHIFTB_7(31 downto 0);
--15:8
when others =>
w1data <= ZEROS(DWIDTH-1 downto 8) & BLANK;
end case;
else
--(NUM_DQ_PINS == 16) (cmd_startC)
--shifting
if (data_mode_i = "0100") then
w1data(127 downto 112) <= "0000000000000000";
w1data(111 downto 96) <= (w1data(107 downto 96) & w1data(111 downto 108));
w1data(95 downto 80) <= "0000000000000000";
w1data(79 downto 64) <= (w1data(75 downto 64) & w1data(79 downto 76));
w1data(63 downto 48) <= "0000000000000000";
w1data(47 downto 32) <= (w1data(43 downto 32) & w1data(47 downto 44));
w1data(31 downto 16) <= "0000000000000000";
w1data(15 downto 0) <= (w1data(11 downto 0) & w1data(15 downto 12));
else
w1data(DWIDTH - 1 downto 0) <= (w1data(4 * DWIDTH / 4 - 9 downto 4 * DWIDTH / 4 - 16) & w1data(4 * DWIDTH / 4 - 1 downto 4 * DWIDTH / 4 - 8) & w1data(4 * DWIDTH / 4 - 25 downto 4 * DWIDTH / 4 - 32) & w1data(4 * DWIDTH / 4 - 17 downto 4 * DWIDTH / 4 - 24) & w1data(3 * DWIDTH / 4 - 9 downto 3 * DWIDTH / 4 - 16) & w1data(3 * DWIDTH / 4 - 1 downto 3 * DWIDTH / 4 - 8) & w1data(3 * DWIDTH / 4 - 25 downto 3 * DWIDTH / 4 - 32) & w1data(3 * DWIDTH / 4 - 17 downto 3 * DWIDTH / 4 - 24) & w1data(2 * DWIDTH / 4 - 9 downto 2 * DWIDTH / 4 - 16) & w1data(2 * DWIDTH / 4 - 1 downto 2 * DWIDTH / 4 - 8) & w1data(2 * DWIDTH / 4 - 25 downto 2 * DWIDTH / 4 - 32) & w1data(2 * DWIDTH / 4 - 17 downto 2 * DWIDTH / 4 - 24) & w1data(1 * DWIDTH / 4 - 9 downto 1 * DWIDTH / 4 - 16) & w1data(1 * DWIDTH / 4 - 1 downto 1 * DWIDTH / 4 - 8) & w1data(1 * DWIDTH / 4 - 25 downto 1 * DWIDTH / 4 - 32) & w1data(1 * DWIDTH / 4 - 17 downto 1 * DWIDTH / 4 - 24));
end if;
end if;
--(DQ_PINS == 16
elsif (NUM_DQ_PINS = 8) then
if (cmd_startC = '1') then -- loading data pattern according the incoming address
if (data_mode_i = "0100") then
w1data <= (BLANK & SHIFT_7 & BLANK & SHIFT_6 & BLANK & SHIFT_5 & BLANK & SHIFT_4 & BLANK & SHIFT_3 & BLANK & SHIFT_2 & BLANK & SHIFT_1 & BLANK & SHIFT_0);
else
w1data <= (SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0 & SHIFT_7 & SHIFT_6 & SHIFT_5 & SHIFT_4 & SHIFT_3 & SHIFT_2 & SHIFT_1 & SHIFT_0); -- (cmd_startC)
end if;
else
-- Shifting
--{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]};
w1data <= w1data; -- else
end if;
--(NUM_DQ_PINS == 8)
elsif (data_mode_i = "0100") then
w1data <= "00001000000001000000001000000001000010000000010000000010000000010000100000000100000000100000000100001000000001000000001000000001";
else
w1data <= "10000100001000011000010000100001100001000010000110000100001000011000010000100001100001000010000110000100001000011000010000100001";
end if;
end if;
end if;
end process;
end generate;
-- HAMMER_PATTERN: Alternating 1s and 0s on DQ pins
-- => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
xhdl7 : if (DWIDTH = 32 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
-- elsif ((fifo_rdy_i = '1' and user_burst_cnt(5 downto 0) /= "000000") or cmd_startC = '1') then
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111"; -- NUM_DQ_PINS == 4
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl8 : if (DWIDTH = 64 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "0000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "0000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "0000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
xhdl9 : if (DWIDTH = 128 and (DATA_PATTERN = "DGEN_HAMMER" or DATA_PATTERN = "DGEN_ALL")) generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i = '1') then
hdata <= (others => '0');
elsif ((fifo_rdy_i = '1' and user_burst_cnt /= 0) or cmd_startC = '1') then
if (NUM_DQ_PINS = 16) then
hdata <= "00000000000000001111111111111111000000000000000011111111111111110000000000000000111111111111111100000000000000001111111111111111";
elsif (NUM_DQ_PINS = 8) then
hdata <= "00000000111111110000000011111111000000001111111100000000111111110000000011111111000000001111111100000000111111110000000011111111";
elsif (NUM_DQ_PINS = 4) then
hdata <= "00001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111000011110000111100001111";
end if;
end if;
end if;
end process;
end generate;
process (w1data, hdata)
begin
for i in 0 to DWIDTH - 1 loop
ndata(i) <= hdata(i) xor w1data(i);
end loop;
end process;
-- HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
-- the position of the pin driving oppsite polarity
-- addr_i[6:2] = 5'h0f ; 32 bit data port
-- => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
-- => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
-- ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
-- => the 1st data pattern : 32'h12345678
-- => the 2nd data pattern : 32'h12345679
-- => the 3rd data pattern : 32'h1234567a
-- => the 4th data pattern : 32'h1234567b
--data_rdy_i
xhdl10 : if (DATA_PATTERN = "DGEN_ADDR" or DATA_PATTERN = "DGEN_ALL") generate
--data_o logic
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmd_startD = '1') then
adata <= addr_i;
elsif ((fifo_rdy_i and data_rdy_i) = '1' and user_burst_cnt > "0000001") then
if (DWIDTH = 128) then
adata <= adata + "00000000000000000000000000010000";
elsif (DWIDTH = 64) then
adata <= adata + "00000000000000000000000000001000"; -- DWIDTH == 32
else
adata <= adata + "00000000000000000000000000000100";
end if;
end if;
end if;
end process;
end generate;
-- PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
-- Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
--
xhdl11 : if (DATA_PATTERN = "DGEN_PRBS" or DATA_PATTERN = "DGEN_ALL") generate
-- PRBS DATA GENERATION
-- xor all the tap positions before feedback to 1st stage.
-- data_clk_en <= fifo_rdy_i and data_rdy_i and to_stdlogicvector(user_burst_cnt > "0000001", 7)(0);
data_clk_en <= (fifo_rdy_i AND data_rdy_i) when (user_burst_cnt > "0000001") ELSE '0';
data_prbs_gen_inst : data_prbs_gen
generic map (
prbs_width => 32,
seed_width => 32
)
port map (
clk_i => clk_i,
clk_en => data_clk_en,
rst_i => rst_i,
prbs_fseed_i => prbs_fseed_i,
prbs_seed_init => cmd_startE,
prbs_seed_i => addr_i(31 downto 0),
prbs_o => prbs_data
);
end generate;
end architecture trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: tg_status.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:42 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
-- Error signal will be asserted if the comparsion is not equal.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity tg_status is
generic (
TCQ : TIME := 100 ps;
DWIDTH : integer := 32
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
manual_clear_error : in std_logic;
data_error_i : in std_logic;
cmp_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
rd_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
cmp_addr_i : in std_logic_vector(31 downto 0);
cmp_bl_i : in std_logic_vector(5 downto 0);
mcb_cmd_full_i : in std_logic;
mcb_wr_full_i : in std_logic;
mcb_rd_empty_i : in std_logic;
error_status : out std_logic_vector(64 + (2 * DWIDTH - 1) downto 0);
error : out std_logic
);
end entity tg_status;
architecture trans of tg_status is
signal data_error_r : std_logic;
signal error_set : std_logic;
begin
error <= error_set;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
data_error_r <= data_error_i;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i or manual_clear_error) = '1') then
-- error_status <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
error_status <= (others => '0');
error_set <= '0';
else
-- latch the first error only
if ((data_error_i and not(data_error_r) and not(error_set)) = '1') then
error_status(31 downto 0) <= cmp_addr_i;
error_status(37 downto 32) <= cmp_bl_i;
error_status(40) <= mcb_cmd_full_i;
error_status(41) <= mcb_wr_full_i;
error_status(42) <= mcb_rd_empty_i;
error_set <= '1';
error_status(64 + (DWIDTH - 1) downto 64) <= cmp_data_i;
error_status(64 + (2 * DWIDTH - 1) downto 64 + DWIDTH) <= rd_data_i;
end if;
error_status(39 downto 38) <= "00"; -- reserved
error_status(63 downto 43) <= "000000000000000000000"; -- reserved
end if;
end if;
end process;
end architecture trans;

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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: wr_data_gen.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose:
-- Reference:
-- Revision History:
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity wr_data_gen is
generic (
TCQ : TIME := 100 ps;
FAMILY : string := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MEM_BURST_LEN : integer := 8;
MODE : string := "WR"; --"WR", "RD"
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic; --
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0); -- "00" = bram;
cmd_rdy_o : out std_logic; -- ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
-- And then it should reasserted when
-- it is generating the last_word.
cmd_valid_i : in std_logic; -- when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
last_word_o : out std_logic;
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- generated address used to determine data pattern.
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0); -- generated burst length for control the burst data
data_rdy_i : in std_logic; -- connect from mcb_wr_full when used as wr_data_gen
-- connect from mcb_rd_empty when used as rd_data_gen
-- When both data_rdy and data_valid is asserted, the ouput data is valid.
data_valid_o : out std_logic; -- connect to wr_en or rd_en and is asserted whenever the
-- pattern is available.
data_o : out std_logic_vector(DWIDTH - 1 downto 0); -- generated data pattern
data_wr_end_o : out std_logic
);
end entity wr_data_gen;
architecture trans of wr_data_gen is
COMPONENT sp6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
COLUMN_WIDTH : INTEGER := 10
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
cmd_startE : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT v6_data_gen IS
GENERIC (
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
MEM_BURST_LEN : integer := 8;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS";
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3;
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
cmd_startA : IN STD_LOGIC;
cmd_startB : IN STD_LOGIC;
cmd_startC : IN STD_LOGIC;
cmd_startD : IN STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH - 1 downto 0);
cmd_startE : IN STD_LOGIC;
m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
user_burst_cnt : IN STD_LOGIC_VECTOR(BL_WIDTH DOWNTO 0);
fifo_rdy_i : IN STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(NUM_DQ_PINS*4 - 1 DOWNTO 0)
);
END COMPONENT;
signal data : std_logic_vector(DWIDTH - 1 downto 0);
signal cmd_rdy : std_logic;
signal cmd_rdyB : std_logic;
signal cmd_rdyC : std_logic;
signal cmd_rdyD : std_logic;
signal cmd_rdyE : std_logic;
signal cmd_rdyF : std_logic;
signal cmd_start : std_logic;
signal cmd_startB : std_logic;
signal cmd_startC : std_logic;
signal cmd_startD : std_logic;
signal cmd_startE : std_logic;
signal cmd_startF : std_logic;
signal burst_count_reached2 : std_logic;
signal data_valid : std_logic;
signal user_burst_cnt : std_logic_vector(6 downto 0);
signal walk_cnt : std_logic_vector(2 downto 0);
signal fifo_not_full : std_logic;
signal i : integer;
signal j : integer;
signal w3data : std_logic_vector(31 downto 0);
-- counter to count user burst length
-- bl_i;
signal u_bcount_2 : std_logic;
signal last_word_t : std_logic;
-- Declare intermediate signals for referenced outputs
signal last_word_o_xhdl1 : std_logic;
signal data_o_xhdl0 : std_logic_vector(DWIDTH - 1 downto 0);
signal tpt_hdata_xhdl2 : std_logic_vector(NUM_DQ_PINS * 4 - 1 downto 0);
begin
-- Drive referenced outputs
last_word_o <= last_word_o_xhdl1;
data_o <= data_o_xhdl0;
fifo_not_full <= data_rdy_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (((user_burst_cnt = "0000010") or (((cmd_start = '1') and (bl_i = "000001")) and FAMILY = "VIRTEX6")) and (fifo_not_full = '1')) then
data_wr_end_o <= '1';
else
data_wr_end_o <= '0';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmd_start <= cmd_validC_i and cmd_rdyC;
cmd_startB <= cmd_valid_i and cmd_rdyB;
cmd_startC <= cmd_validB_i and cmd_rdyC;
cmd_startD <= cmd_validB_i and cmd_rdyD;
cmd_startE <= cmd_validB_i and cmd_rdyE;
cmd_startF <= cmd_validB_i and cmd_rdyF;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
user_burst_cnt <= "0000000" ;
elsif (cmd_start = '1') then
if (FAMILY = "SPARTAN6") then
if (bl_i = "000000") then
user_burst_cnt <= "1000000" ;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
else
user_burst_cnt <= ('0' & bl_i) ;
end if;
elsif (fifo_not_full = '1') then
if (user_burst_cnt /= "0000000") then
user_burst_cnt <= user_burst_cnt - "0000001" ;
else
user_burst_cnt <= "0000000" ;
end if;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((user_burst_cnt = "0000010" and fifo_not_full = '1') or (cmd_startC = '1' and bl_i = "000001")) then
u_bcount_2 <= '1' ;
elsif (last_word_o_xhdl1 = '1') then
u_bcount_2 <= '0' ;
end if;
end if;
end process;
last_word_o_xhdl1 <= u_bcount_2 and fifo_not_full;
-- cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
-- is assert and reassert during the last data
cmd_rdy_o <= cmd_rdy and fifo_not_full;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdy <= '1' ;
elsif (cmd_start = '1') then
if (bl_i = "000001") then
cmd_rdy <= '1' ;
else
cmd_rdy <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdy <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyB <= '1' ;
elsif (cmd_startB = '1') then
if (bl_i = "000001") then
cmd_rdyB <= '1' ;
else
cmd_rdyB <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyB <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyC <= '1' ;
elsif (cmd_startC = '1') then
if (bl_i = "000001") then
cmd_rdyC <= '1' ;
else
cmd_rdyC <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyC <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyD <= '1' ;
elsif (cmd_startD = '1') then
if (bl_i = "000001") then
cmd_rdyD <= '1' ;
else
cmd_rdyD <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyD <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyE <= '1' ;
elsif (cmd_startE = '1') then
if (bl_i = "000001") then
cmd_rdyE <= '1' ;
else
cmd_rdyE <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyE <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(0)) = '1') then
cmd_rdyF <= '1' ;
elsif (cmd_startF = '1') then
if (bl_i = "000001") then
cmd_rdyF <= '1' ;
else
cmd_rdyF <= '0' ;
end if;
elsif (user_burst_cnt = "0000010" and fifo_not_full = '1') then
cmd_rdyF <= '1' ;
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if ((rst_i(1)) = '1') then
data_valid <= '0' ;
elsif (cmd_start = '1') then
data_valid <= '1' ;
elsif (fifo_not_full = '1' and user_burst_cnt <= "0000001") then
data_valid <= '0' ;
end if;
end if;
end process;
data_valid_o <= data_valid and fifo_not_full;
s6_wdgen : if (FAMILY = "SPARTAN6") generate
sp6_data_gen_inst : sp6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
COLUMN_WIDTH => COLUMN_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_startA => cmd_start,
cmd_startB => cmd_startB,
cmd_startC => cmd_startC,
cmd_startD => cmd_startD,
cmd_startE => cmd_startE,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
v6_wdgen : if (FAMILY = "VIRTEX6") generate
v6_data_gen_inst : v6_data_gen
generic map (
ADDR_WIDTH => 32,
BL_WIDTH => BL_WIDTH,
DWIDTH => DWIDTH,
MEM_BURST_LEN => MEM_BURST_LEN,
DATA_PATTERN => DATA_PATTERN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
COLUMN_WIDTH => COLUMN_WIDTH,
EYE_TEST => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(1),
data_rdy_i => data_rdy_i,
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_starta => cmd_start,
cmd_startb => cmd_startB,
cmd_startc => cmd_startC,
cmd_startd => cmd_startD,
cmd_starte => cmd_startE,
fixed_data_i => fixed_data_i,
m_addr_i => addr_i, --m_addr_i,
addr_i => addr_i,
user_burst_cnt => user_burst_cnt,
fifo_rdy_i => fifo_not_full,
data_o => data_o_xhdl0
);
end generate;
end architecture trans;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/rtl/traffic_gen/write_data_path.vhd vendored Executable file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;

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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : isim.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run Simulation through ISIM
# Reference :
# Revision History :
# ****************************************************************************
echo Simulation Tool: ISIM
fuse work.sim_tb_top work.glbl -prj ddr2.prj -L unisim -L secureip -timeprecision_vhdl fs -o ddr2
./ddr2 -gui -tclbatch isim.tcl -wdb ddr2.wdb
echo done

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/isim.tcl vendored Executable file
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###############################################################################
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.92
## \ \ Application : MIG
## / / Filename : isim.tcl
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
## \ \ / \ Date Created : Mon Mar 2 2009
## \___\/\___\
##
## Device : Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose : To give commands to ISIM Simulator through batch mode
## Assumptions:
## - Simulation takes place in \sim folder of MIG output directory
## Reference :
## Revision History:
###############################################################################
onerror {resume}
isim set radix hex
wave add /sim_tb_top
run 200 us
quit

131
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/readme.txt vendored Executable file
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###############################################################################
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.92
## \ \ Application : MIG
## / / Filename : readme.txt
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
## \ \ / \ Date Created : Mon Oct 19 2009
## \___\/\___\
##
## Device : Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose : Steps to run simulation using ISIM/Modelsim simualtor in this folder
## Assumptions:
## - Simulation takes place in \sim\<functional/timing> folder of MIG output directory
## Reference :
## Revision History:
###############################################################################
The sim/functional folder has files to perform functional simulation of the design.
1. Simulation using Modelsim simulator
A) sim.do File :
1) The 'sim.do' file has commands to compile and simulate memory interface
design and run the simulation for specified period of time.
2) It has the syntax to Map the required libraries.
Also, $XILINX environment variable must be set in order to compile glbl.v file
3) Displays the waveforms that are listed with "add wave" command.
B) Steps to run the Modelsim simulation:
1) The user should invoke the Modelsim simulator GUI.
2) Change the present working directory path to the sim/functional folder.
In Transcript window, at Modelsim prompt, type the following command to
change directory path.
cd <sim/functional directory path>
2) Run the simulation using sim.do file.
At Modelsim prompt, type the following command:
do sim.do
3) To exit simulation, type the following command at Modelsim prompt:
quit -f
4) Verify the transcript file for the memory transactions.
C) For simulation with Elpida parts perform the following steps and then
the above mentioned steps in 'B'
1) Download the Elpida memory model from Elpida webpage.
2) Update the memorymodel name in the vlog command given in sim.do file.
2. Simulation using ISIM simulator
A) Following files are provided :
1) The '.prj' file contains the list of all the files associated with the design.
It also contains the hdl, library and the source file name.
2) The '.tcl' file contains the Tcl commands for simulation and
resume on error.
3) The 'isim.bat' has commands which use '.prj' and '.tcl' files.
B) Steps to run the ISIM simulation:
The user should execute the file isim.bat, which does the following steps:
1) Compiles, elaborates the design and generates the simulation executable using
the fuse command in 'isim.bat' file.
2) Invokes the ISIM GUI.
3) User can add required signals from objects window to the waveform viewer and run
simulation for specified time using the command "run <time>" in ISIM GUI.
C) Simulations using ISIM simulator is not supported for Elpida parts.

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###############################################################################
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
###############################################################################
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.92
## \ \ Application : MIG
## / / Filename : sim.do
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
## \ \ / \ Date Created : Mon Mar 2 2009
## \___\/\___\
##
## Device: Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose:
## Sample sim .do file to compile and simulate memory interface
## design and run the simulation for specified period of time. Display the
## waveforms that are listed with "add wave" command.
## Assumptions:
## - Simulation takes place in \sim folder of MIG output directory
## Reference:
## Revision History:
###############################################################################
vlib work
#Map the required libraries here.#
#vmap unisim <unisim lib path>
#vmap secureip <secureip lib path>
#Compile all rtl modules#
vcom ../../rtl/*.vhd
#Compile all traffic_gen modules#
vcom ../../rtl/traffic_gen/*.vhd
#Compile files in sim folder (excluding model parameter file)#
#$XILINX variable must be set
vlog $env(XILINX)/verilog/src/glbl.v
vcom ../functional/*.vhd
#Pass the parameters for memory model parameter file#
vlog +incdir+. +define+x1Gb +define+sg25E +define+x16 ddr2_model_c3.v
#Load the design. Use required libraries.#
vsim -t ps -novopt +notimingchecks -L unisim -L secureip work.sim_tb_top glbl
onerror {resume}
#Log all the objects in design. These will appear in .wlf file#
log -r /*
#View sim_tb_top signals in waveform#
add wave sim:/sim_tb_top/*
#Change radix to Hexadecimal#
radix hex
#Supress Numeric Std package and Arith package warnings.#
#For VHDL designs we get some warnings due to unknown values on some signals at startup#
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0#
#We may also get some Arithmetic packeage warnings because of unknown values on#
#some of the signals that are used in an Arithmetic operation.#
#In order to suppress these warnings, we use following two commands#
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
#Choose simulation run time by inserting a breakpoint and then run for specified #
#period. Refer simulation_help file.#
when {/sim_tb_top/design_top/calib_done = 1} {
echo "Calibration Done"
if {[when -label a_100] == ""} {
when -label a_100 { $now = 50 us } {
nowhen a_100
report simulator control
report simulator state
if {[examine /sim_tb_top/design_top/error] == 0} {
echo "TEST PASSED"
stop
}
if {[examine /sim_tb_top/design_top/error] != 0} {
echo "TEST FAILED: DATA ERROR"
stop
}
}
}
}
#In case calibration fails to complete, choose the run time and then quit#
when {$now = @500 us and /sim_tb_top/design_top/calib_done != 1} {
echo "TEST FAILED: INITIALIZATION DID NOT COMPLETE"
stop
}
run -all
stop

445
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/sim_tb_top.vhd vendored Normal file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 13;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic
);
end component;
component ddr2_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_rdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
rdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
signal zio3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr2_model_c3 port map(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_rdqs => mcb3_dram_dm_vector ,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
rdqs_n => open,
odt => mcb3_dram_odt
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;

72
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/sim/functional/timing_sim.sh vendored Executable file
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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : timing_sim.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to generate simulation netlist file.
# Reference :
# Revision History :
# ****************************************************************************
echo Simulation Tool: TIMING SIMULATION
cd ../../par
./ise_flow.bat
echo Netlist Generated
cd ../sim/timing
echo done

36
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/mem_interface_top_synp.sdc vendored Normal file
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# Synplicity, Inc. constraint file
# Written on Mon Jun 27 15:50:39 2005
define_attribute {v:work.example_top} syn_hier {hard}
define_attribute {v:work.iodrp_controller} syn_hier {hard}
define_attribute {v:work.iodrp_mcb_controller} syn_hier {hard}
define_attribute {v:work.mcb_raw_wrapper} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration} syn_hier {hard}
define_attribute {v:work.mcb_soft_calibration_top} syn_hier {hard}
define_attribute {v:work.memc3_infrastructure} syn_hier {hard}
define_attribute {v:work.memc3_tb_top} syn_hier {hard}
define_attribute {v:work.memc3_wrapper} syn_hier {hard}
define_attribute {v:work.afifo} syn_hier {hard}
define_attribute {v:work.cmd_gen} syn_hier {hard}
define_attribute {v:work.cmd_prbs_gen} syn_hier {hard}
define_attribute {v:work.data_prbs_gen} syn_hier {hard}
define_attribute {v:work.init_mem_pattern_ctr} syn_hier {hard}
define_attribute {v:work.mcb_flow_control} syn_hier {hard}
define_attribute {v:work.mcb_traffic_gen} syn_hier {hard}
define_attribute {v:work.rd_data_gen} syn_hier {hard}
define_attribute {v:work.read_data_path} syn_hier {hard}
define_attribute {v:work.read_posted_fifo} syn_hier {hard}
define_attribute {v:work.sp6_data_gen} syn_hier {hard}
define_attribute {v:work.tg_status} syn_hier {hard}
define_attribute {v:work.v6_data_gen} syn_hier {hard}
define_attribute {v:work.wr_data_gen} syn_hier {hard}
define_attribute {v:work.write_data_path} syn_hier {hard}
# clock Constraints
define_clock -disable -name {memc3_infrastructure_inst} -period 3000 -clockgroup default_clkgroup_1
define_clock -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3000 -clockgroup default_clkgroup_2
define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3000 -clockgroup default_clkgroup_3

56
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/example_design/synth/script_synp.tcl vendored Normal file
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project -new
add_file -vhdl "../rtl/example_top.vhd"
add_file -vhdl "../rtl/iodrp_controller.vhd"
add_file -vhdl "../rtl/iodrp_mcb_controller.vhd"
add_file -vhdl "../rtl/mcb_raw_wrapper.vhd"
add_file -vhdl "../rtl/mcb_soft_calibration.vhd"
add_file -vhdl "../rtl/mcb_soft_calibration_top.vhd"
add_file -vhdl "../rtl/memc3_infrastructure.vhd"
add_file -vhdl "../rtl/memc3_tb_top.vhd"
add_file -vhdl "../rtl/memc3_wrapper.vhd"
add_file -vhdl "../rtl/traffic_gen/afifo.vhd"
add_file -vhdl "../rtl/traffic_gen/cmd_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/cmd_prbs_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/data_prbs_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/init_mem_pattern_ctr.vhd"
add_file -vhdl "../rtl/traffic_gen/mcb_flow_control.vhd"
add_file -vhdl "../rtl/traffic_gen/mcb_traffic_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/rd_data_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/read_data_path.vhd"
add_file -vhdl "../rtl/traffic_gen/read_posted_fifo.vhd"
add_file -vhdl "../rtl/traffic_gen/sp6_data_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/tg_status.vhd"
add_file -vhdl "../rtl/traffic_gen/v6_data_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/wr_data_gen.vhd"
add_file -vhdl "../rtl/traffic_gen/write_data_path.vhd"
add_file -constraint "../synth/mem_interface_top_synp.sdc"
impl -add rev_1
set_option -technology spartan6
set_option -part xc6slx45
set_option -package csg324
set_option -speed_grade -3
set_option -default_enum_encoding default
#AXI_ENABLE synp definition is not required for user_design
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "example_top"
set_option -frequency 333.333
set_option -fanout_limit 1000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -fixgatedclocks 0
set_option -retiming 0
set_option -modular 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -write_apr_constraint 0
project -result_file "../synth/rev_1/example_top.edf"
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "../synth/rev_1"
project -run
project -save

72
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/datasheet.txt vendored Normal file
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@@ -0,0 +1,72 @@
CORE Generator Options:
Target Device : xc6slx45-csg324
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : ddr2
No of Controllers : 1
Hardware Test Bench : disabled
/*******************************************************/
/* Controller 3 */
/*******************************************************/
Controller Options :
Memory : DDR2_SDRAM
Interface : NATIVE
Design Clock Frequency : 3000 ps (333.33 MHz)
Memory Type : Components
Memory Part : MT47H64M16XX-25E
Equivalent Part(s) : MT47H64M16HR-25E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 4(010)
CAS Latency : 5
DQS# Enable : Enable
DLL Enable : Enable-Normal
OCD Operation : OCD Exit
Output Drive Strength : Fullstrength
Outputs : Enable
Additive Latency (AL) : 0
RDQS Enable : Disable
RTT (nominal) - ODT : 50ohms
High Temparature Self Refresh Rate : Disable
User Interface Parameters :
Configuration Type : Four 32-bit bi-directional ports
Ports Selected : Port0, Port1, Port2, Port3
Memory Address Mapping : BANK_ROW_COLUMN
Arbitration Algorithm : Round Robin
Arbitration :
Time Slot0 : 0123
Time Slot1 : 1230
Time Slot2 : 2301
Time Slot3 : 3012
Time Slot4 : 0123
Time Slot5 : 1230
Time Slot6 : 2301
Time Slot7 : 3012
Time Slot8 : 0123
Time Slot9 : 1230
Time Slot10: 2301
Time Slot11: 3012
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : CALIB_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended

72
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/create_ise.sh vendored Executable file
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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : create_ise.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
xtclsh set_ise_prop.tcl

163
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ddr2.ucf vendored Normal file
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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Sun Jul 28 12:10:25 2013
## Generated by MIG Version 3.92
##
############################################################################
## File name : ddr2.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx45-csg324
## Speedgrade: -3
## Design Entry: VHDL
## Design: without Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# VCC AUX VOLTAGE
############################################################################
CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3
############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "c?_pll_lock" TIG;
INST "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
#Please uncomment the below TIG if used in a design which enables self-refresh mode
#NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG; ## This path exists for DDR2 only
############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47H64M16XX-25E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
## Supported Part Numbers: MT47H64M16HR-25E
############################################################################
############################################################################
## Clock constraints
############################################################################
NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 3 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II ;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II ;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II ;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II ;
NET "mcb3_zio" IOSTANDARD = SSTL18_II ;
NET "c3_sys_clk" IOSTANDARD = LVCMOS25 ;
NET "c3_sys_rst_i" IOSTANDARD = LVCMOS18 ;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "mcb3_dram_a[0]" LOC = "J7" ;
NET "mcb3_dram_a[10]" LOC = "F4" ;
NET "mcb3_dram_a[11]" LOC = "D3" ;
NET "mcb3_dram_a[12]" LOC = "G6" ;
NET "mcb3_dram_a[1]" LOC = "J6" ;
NET "mcb3_dram_a[2]" LOC = "H5" ;
NET "mcb3_dram_a[3]" LOC = "L7" ;
NET "mcb3_dram_a[4]" LOC = "F3" ;
NET "mcb3_dram_a[5]" LOC = "H4" ;
NET "mcb3_dram_a[6]" LOC = "H3" ;
NET "mcb3_dram_a[7]" LOC = "H6" ;
NET "mcb3_dram_a[8]" LOC = "D2" ;
NET "mcb3_dram_a[9]" LOC = "D1" ;
NET "mcb3_dram_ba[0]" LOC = "F2" ;
NET "mcb3_dram_ba[1]" LOC = "F1" ;
NET "mcb3_dram_ba[2]" LOC = "E1" ;
NET "mcb3_dram_cas_n" LOC = "K5" ;
NET "mcb3_dram_ck" LOC = "G3" ;
NET "mcb3_dram_ck_n" LOC = "G1" ;
NET "mcb3_dram_cke" LOC = "H7" ;
NET "mcb3_dram_dm" LOC = "K3" ;
NET "mcb3_dram_dq[0]" LOC = "L2" ;
NET "mcb3_dram_dq[10]" LOC = "N2" ;
NET "mcb3_dram_dq[11]" LOC = "N1" ;
NET "mcb3_dram_dq[12]" LOC = "T2" ;
NET "mcb3_dram_dq[13]" LOC = "T1" ;
NET "mcb3_dram_dq[14]" LOC = "U2" ;
NET "mcb3_dram_dq[15]" LOC = "U1" ;
NET "mcb3_dram_dq[1]" LOC = "L1" ;
NET "mcb3_dram_dq[2]" LOC = "K2" ;
NET "mcb3_dram_dq[3]" LOC = "K1" ;
NET "mcb3_dram_dq[4]" LOC = "H2" ;
NET "mcb3_dram_dq[5]" LOC = "H1" ;
NET "mcb3_dram_dq[6]" LOC = "J3" ;
NET "mcb3_dram_dq[7]" LOC = "J1" ;
NET "mcb3_dram_dq[8]" LOC = "M3" ;
NET "mcb3_dram_dq[9]" LOC = "M1" ;
NET "mcb3_dram_dqs" LOC = "L4" ;
NET "mcb3_dram_dqs_n" LOC = "L3" ;
NET "mcb3_dram_odt" LOC = "K6" ;
NET "mcb3_dram_ras_n" LOC = "L5" ;
NET "c3_sys_clk" LOC = "R10" ;
NET "c3_sys_rst_i" LOC = "M8" ;
NET "mcb3_dram_udm" LOC = "K4" ;
NET "mcb3_dram_udqs" LOC = "P2" ;
NET "mcb3_dram_udqs_n" LOC = "P1" ;
NET "mcb3_dram_we_n" LOC = "E3" ;
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_rzq" LOC = "N4" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_zio" LOC = "P4" ;

48
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/icon_coregen.xco vendored Normal file
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##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 07:09:11 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
# END Select
# BEGIN Parameters
CSET component_name=icon
CSET enable_jtag_bufg=true
CSET number_control_ports=2
CSET use_ext_bscan=false
CSET use_softbscan=false
CSET use_unused_bscan=false
CSET user_scan_chain=USER1
# END Parameters
GENERATE
# CRC: 7da1f376

131
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ila_coregen.xco vendored Normal file
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##############################################################
#
# Xilinx Core Generator version 11.1
# Date: Wed Mar 11 06:55:40 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET component_name=ila
CSET counter_width_1=Disabled
CSET counter_width_10=Disabled
CSET counter_width_11=Disabled
CSET counter_width_12=Disabled
CSET counter_width_13=Disabled
CSET counter_width_14=Disabled
CSET counter_width_15=Disabled
CSET counter_width_16=Disabled
CSET counter_width_2=Disabled
CSET counter_width_3=Disabled
CSET counter_width_4=Disabled
CSET counter_width_5=Disabled
CSET counter_width_6=Disabled
CSET counter_width_7=Disabled
CSET counter_width_8=Disabled
CSET counter_width_9=Disabled
CSET data_port_width=256
CSET data_same_as_trigger=false
CSET enable_storage_qualification=true
CSET enable_trigger_output_port=false
CSET exclude_from_data_storage_1=true
CSET exclude_from_data_storage_10=true
CSET exclude_from_data_storage_11=true
CSET exclude_from_data_storage_12=true
CSET exclude_from_data_storage_13=true
CSET exclude_from_data_storage_14=true
CSET exclude_from_data_storage_15=true
CSET exclude_from_data_storage_16=true
CSET exclude_from_data_storage_2=true
CSET exclude_from_data_storage_3=true
CSET exclude_from_data_storage_4=true
CSET exclude_from_data_storage_5=true
CSET exclude_from_data_storage_6=true
CSET exclude_from_data_storage_7=true
CSET exclude_from_data_storage_8=true
CSET exclude_from_data_storage_9=true
CSET match_type_1=basic_with_edges
CSET match_type_10=basic
CSET match_type_11=basic
CSET match_type_12=basic
CSET match_type_13=basic
CSET match_type_14=basic
CSET match_type_15=basic
CSET match_type_16=basic
CSET match_type_2=basic
CSET match_type_3=basic
CSET match_type_4=basic
CSET match_type_5=basic
CSET match_type_6=basic
CSET match_type_7=basic
CSET match_type_8=basic
CSET match_type_9=basic
CSET match_units_1=1
CSET match_units_10=1
CSET match_units_11=1
CSET match_units_12=1
CSET match_units_13=1
CSET match_units_14=1
CSET match_units_15=1
CSET match_units_16=1
CSET match_units_2=1
CSET match_units_3=1
CSET match_units_4=1
CSET match_units_5=1
CSET match_units_6=1
CSET match_units_7=1
CSET match_units_8=1
CSET match_units_9=1
CSET max_sequence_levels=1
CSET number_of_trigger_ports=1
CSET sample_data_depth=1024
CSET sample_on=Rising
CSET trigger_port_width_1=2
CSET trigger_port_width_10=8
CSET trigger_port_width_11=8
CSET trigger_port_width_12=8
CSET trigger_port_width_13=8
CSET trigger_port_width_14=8
CSET trigger_port_width_15=8
CSET trigger_port_width_16=8
CSET trigger_port_width_2=8
CSET trigger_port_width_3=8
CSET trigger_port_width_4=8
CSET trigger_port_width_5=8
CSET trigger_port_width_6=8
CSET trigger_port_width_7=8
CSET trigger_port_width_8=8
CSET trigger_port_width_9=8
CSET use_rpms=true
# END Parameters
GENERATE
# CRC: eff89f81

86
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_flow.sh vendored Executable file
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#!/bin/csh -f
#*****************************************************************************
# (c) Copyright 2009 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
# ****************************************************************************
# ____ ____
# / /\/ /
# /___/ \ / Vendor : Xilinx
# \ \ \/ Version : 3.92
# \ \ Application : MIG
# / / Filename : ise_flow.bat
# /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
# \ \ / \ Date Created : Fri Feb 06 2009
# \___\/\___\
#
# Device : Spartan-6
# Design Name : DDR/DDR2/DDR3/LPDDR
# Purpose : Batch file to run PAR through ISE batch mode
# Reference :
# Revision History :
# ****************************************************************************
./rem_files.sh
echo Synthesis Tool: XST
mkdir "../synth/__projnav" > ise_flow_results.txt
mkdir "../synth/xst" >> ise_flow_results.txt
mkdir "../synth/xst/work" >> ise_flow_results.txt
xst -ifn ise_run.txt -ofn mem_interface_top.syr -intstyle ise >> ise_flow_results.txt
ngdbuild -intstyle ise -dd ../synth/_ngo -uc ddr2.ucf -p xc6slx45csg324-3 ddr2.ngc ddr2.ngd >> ise_flow_results.txt
map -intstyle ise -detail -w -pr off -c 100 -o ddr2_map.ncd ddr2.ngd ddr2.pcf >> ise_flow_results.txt
par -w -intstyle ise -ol std ddr2_map.ncd ddr2.ncd ddr2.pcf >> ise_flow_results.txt
trce -e 100 ddr2.ncd ddr2.pcf >> ise_flow_results.txt
bitgen -intstyle ise -f mem_interface_top.ut ddr2.ncd >> ise_flow_results.txt
echo done!

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/ise_run.txt vendored Normal file
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set -tmpdir ../synth/__projnav
set -xsthdpdir ../synth/xst
run
#Source Parameters
-ifn ../synth/ddr2.prj
-ifmt mixed
-iuc No
#Target Parameters
-ofn ddr2
-ofmt NGC
-p xc6slx45-3csg324
#AXI_ENABLE definition is not required for NATIVE interface
#Source Options
-top ddr2
-fsm_extract Yes
-fsm_encoding one-hot
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-rom_style Auto
-shreg_extract Yes
-resource_sharing Yes
-async_to_sync no
-mult_style auto
-register_balancing No
#Target Options
-iobuf Yes
#Max fanout value shouldn't be set below 64 for MCB design
-max_fanout 500
-bufg 16
-register_duplication yes
-optimize_primitives No
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal yes
#General Options
-opt_mode Speed
-opt_level 1
-lso ../synth/ddr2.lso
-keep_hierarchy NO
-netlist_hierarchy as_optimized
-rtlview Yes
-glob_opt allclocknets
-read_cores Yes
-write_timing_constraints No
-cross_clock_analysis No
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-auto_bram_packing No
-slice_utilization_ratio_maxmargin 5
quit

2
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/makeproj.sh vendored Executable file
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NEWPROJECT .
SETPROJECT .

22
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/mem_interface_top.ut vendored Normal file
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-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullNone
-g UserID:0xFFFFFFFF
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:No
-g DriveDone:No
-g ConfigRate:6

146
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/readme.txt vendored Normal file
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::****************************************************************************
:: (c) Copyright 2009 Xilinx, Inc. All rights reserved.
::
:: This file contains confidential and proprietary information
:: of Xilinx, Inc. and is protected under U.S. and
:: international copyright and other intellectual property
:: laws.
::
:: DISCLAIMER
:: This disclaimer is not a license and does not grant any
:: rights to the materials distributed herewith. Except as
:: otherwise provided in a valid license issued to you by
:: Xilinx, and to the maximum extent permitted by applicable
:: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
:: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
:: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
:: (2) Xilinx shall not be liable (whether in contract or tort,
:: including negligence, or under any other theory of
:: liability) for any loss or damage of any kind or nature
:: related to, arising under or in connection with these
:: materials, including for any direct, or any indirect,
:: special, incidental, or consequential loss or damage
:: (including loss of data, profits, goodwill, or any type of
:: loss or damage suffered as a result of any action brought
:: by a third party) even if such damage or loss was
:: reasonably foreseeable or Xilinx had been advised of the
:: possibility of the same.
::
:: CRITICAL APPLICATIONS
:: Xilinx products are not designed or intended to be fail-
:: safe, or for use in any application requiring fail-safe
:: performance, such as life-support or safety devices or
:: systems, Class III medical devices, nuclear facilities,
:: applications related to the deployment of airbags, or any
:: other applications that could lead to death, personal
:: injury, or severe property or environmental damage
:: (individually and collectively, "Critical
:: Applications"). Customer assumes the sole risk and
:: liability of any use of Xilinx products in Critical
:: Applications, subject only to applicable laws and
:: regulations governing limitations on product liability.
::
:: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
:: PART OF THIS FILE AT ALL TIMES.
::
::****************************************************************************
:: ____ ____
:: / /\/ /
:: /___/ \ / Vendor : Xilinx
:: \ \ \/ Version : 3.92
:: \ \ Application : MIG
:: / / Filename : readme.txt
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
:: \ \ / \ Date Created : Fri Feb 06 2009
:: \___\/\___\
::
:: Device : Spartan-6
:: Design Name : DDR/DDR2/DDR3/LPDDR
:: Purpose : Information about par folder
:: Reference :
:: Revision History :
::****************************************************************************
This folder has the batch files to synthesize using XST or Synplify Pro and
implement the design either in "Command Line Mode" or in "GUI Mode".
Steps to run the design using the ise_flow (batch mode):
1. Executing the "ise_flow.bat" file synthesizes the design using XST or
Synplify Pro and does implement the design.
a. First it removes the XST/Synplify Pro report files, implementation
files, supporting scripts, the generated chipscope designs (if
enabled) and the ISE project files (if exist any on previous runs)
b. Synthesizes the design either with XST or Synplicity
c. Implements the design with ISE.
2. After the design is run, it creates ise_flow_results.txt file that will have
the ISE log information.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.bat" file creates "test.xise" project file
and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing the command
'ise test.xise' from the terminal.
Other files in PAR folder :
* "ddr2.ucf" file is the constraint file for the design.
It has clock constraints, location constraints and IO standards.
* "mem_interface_top.ut" file has the options for the Configuration file
generation i.e. the "ddr2.bit" file to run in batch mode.
* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
implementation files, supporting scripts, the generated chipscope designs
(if enabled) and the ISE project files.
* "set_ise_prop.tcl" file has all the properties that are to be
set in GUI mode.
* "ise_run.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
EDIF/NGC files, you must execute the following commands before starting
synthesis and PAR.
coregen -b ila_coregen.xco
coregen -b icon_coregen.xco
coregen -b vio_coregen.xco
Note : When you generate the design using "Debug Signals for Memory Controller"
option Enable, the above mentioned ChipScope coregen commands are printed
into ise_flow.bat and create_ise.bat files. The ddr2 rtl file
will have the design debug signals portmapped to vio and icon
ChipScope modules.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "ddr2.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "ddr2.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
For Multiple Controller designs, signal names provided in CDC file are of
the controller that is enabled for Debug in the GUI.
synth folder:
1. mem_interface_top_synp.sdc
2. script_synp.tcl
3. ddr2.prj
4. ddr2.lso
mem_interface_top_synp.sdc and script_synp.tcl files are being used by
Synplify Pro and ddr2.prj and ddr2.lso are being used by XST.

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/rem_files.sh vendored Executable file
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##!/bin/csh -f
##****************************************************************************
## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
##
## This file contains confidential and proprietary information
## of Xilinx, Inc. and is protected under U.S. and
## international copyright and other intellectual property
## laws.
##
## DISCLAIMER
## This disclaimer is not a license and does not grant any
## rights to the materials distributed herewith. Except as
## otherwise provided in a valid license issued to you by
## Xilinx, and to the maximum extent permitted by applicable
## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
## (2) Xilinx shall not be liable (whether in contract or tort,
## including negligence, or under any other theory of
## liability) for any loss or damage of any kind or nature
## related to, arising under or in connection with these
## materials, including for any direct, or any indirect,
## special, incidental, or consequential loss or damage
## (including loss of data, profits, goodwill, or any type of
## loss or damage suffered as a result of any action brought
## by a third party) even if such damage or loss was
## reasonably foreseeable or Xilinx had been advised of the
## possibility of the same.
##
## CRITICAL APPLICATIONS
## Xilinx products are not designed or intended to be fail-
## safe, or for use in any application requiring fail-safe
## performance, such as life-support or safety devices or
## systems, Class III medical devices, nuclear facilities,
## applications related to the deployment of airbags, or any
## other applications that could lead to death, personal
## injury, or severe property or environmental damage
## (individually and collectively, "Critical
## Applications"). Customer assumes the sole risk and
## liability of any use of Xilinx products in Critical
## Applications, subject only to applicable laws and
## regulations governing limitations on product liability.
##
## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
## PART OF THIS FILE AT ALL TIMES.
##
##****************************************************************************
## ____ ____
## / /\/ /
## /___/ \ / Vendor : Xilinx
## \ \ \/ Version : 3.92
## \ \ Application : MIG
## / / Filename : rem_files.bat
## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:55 $
## \ \ / \ Date Created : Fri Feb 06 2009
## \___\/\___\
##
## Device : Spartan-6
## Design Name : DDR/DDR2/DDR3/LPDDR
## Purpose : Batch file to remove files generated from ISE
## Reference :
## Revision History :
##****************************************************************************
rm -rf "../synth/__projnav"
rm -rf "../synth/xst"
rm -rf "../synth/_ngo"
rm -rf tmp
rm -rf _xmsgs
rm -rf ila_xdb
rm -rf icon_xdb
rm -rf vio_xdb
rm -rf xlnx_auto_0_xdb
rm -rf vio_xmdf.tcl
rm -rf vio_readme.txt
rm -rf vio_flist.txt
rm -rf vio.xise del
rm -rf vio.xco del
rm -rf vio.ngc del
rm -rf vio.ise del
rm -rf vio.gise del
rm -rf vio.cdc del
rm -rf coregen.cgp
rm -rf coregen.cgc
rm -rf coregen.log
rm -rf ila.cdc
rm -rf ila.gise
rm -rf ila.ise
rm -rf ila.ngc
rm -rf ila.xco
rm -rf ila.xise
rm -rf ila_flist.txt
rm -rf ila_readme.txt
rm -rf ila_xmdf.tcl
rm -rf icon.asy
rm -rf icon.gise
rm -rf icon.ise
rm -rf icon.ncf
rm -rf icon.ngc
rm -rf icon.xco
rm -rf icon.xise
rm -rf icon_flist.txt
rm -rf icon_readme.txt
rm -rf icon_xmdf.tcl
rm -rf ise_flow_results.txt
rm -rf ddr2_vhdl.prj
rm -rf mem_interface_top.syr
rm -rf ddr2.ngc
rm -rf ddr2.ngr
rm -rf ddr2_xst.xrpt
rm -rf ddr2.bld
rm -rf ddr2.ngd
rm -rf ddr2_ngdbuild.xrpt
rm -rf ddr2_map.map
rm -rf ddr2_map.mrp
rm -rf ddr2_map.ngm
rm -rf ddr2.pcf
rm -rf ddr2_map.ncd
rm -rf ddr2_map.xrpt
rm -rf ddr2_summary.xml
rm -rf ddr2_usage.xml
rm -rf ddr2.ncd
rm -rf ddr2.par
rm -rf ddr2.xpi
rm -rf ddr2.ptwx
rm -rf ddr2.pad
rm -rf ddr2.unroutes
rm -rf ddr2_pad.csv
rm -rf ddr2_pad.txt
rm -rf ddr2_par.xrpt
rm -rf ddr2.twx
rm -rf ddr2.bgn
rm -rf ddr2.twr
rm -rf ddr2.drc
rm -rf ddr2_bitgen.xwbt
rm -rf ddr2.bit
# Files and folders generated by create ise
rm -rf test_xdb
rm -rf _xmsgs
rm -rf test.gise
rm -rf test.xise
rm -rf test.xise
# Files and folders generated by ISE through GUI mode
rm -rf _ngo
rm -rf xst
rm -rf ddr2.lso
rm -rf ddr2.prj
rm -rf ddr2.xst
rm -rf ddr2.stx
rm -rf ddr2_prev_built.ngd
rm -rf test.ntrc_log
rm -rf ddr2_guide.ncd
rm -rf ddr2.cmd_log
rm -rf ddr2_summary.html
rm -rf ddr2.ut
rm -rf par_usage_statistics.html
rm -rf usage_statistics_webtalk.html
rm -rf webtalk.log
rm -rf device_usage_statistics.html

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/set_ise_prop.tcl vendored Normal file
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project new test.xise
project set "Device Family" "spartan6"
project set "Device" "xc6slx45"
project set "Package" "csg324"
project set "Speed Grade" "-3"
project set "Synthesis Tool" "XST (VHDL/Verilog)"
project set "Simulator" "ISim (VHDL/Verilog)"
xfile add "../rtl/ddr2.vhd"
xfile add "../rtl/iodrp_controller.vhd"
xfile add "../rtl/iodrp_mcb_controller.vhd"
xfile add "../rtl/mcb_raw_wrapper.vhd"
xfile add "../rtl/mcb_soft_calibration.vhd"
xfile add "../rtl/mcb_soft_calibration_top.vhd"
xfile add "../rtl/memc3_infrastructure.vhd"
xfile add "../rtl/memc3_wrapper.vhd"
xfile add "ddr2.ucf"
project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "FSM Style" "LUT" -process "Synthesize - XST"
project set "RAM Extraction" "True" -process "Synthesize - XST"
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "ROM Extraction" "True" -process "Synthesize - XST"
project set "ROM Style" "Auto" -process "Synthesize - XST"
project set "Resource Sharing" "True" -process "Synthesize - XST"
project set "Asynchronous To Synchronous" "False" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Add I/O Buffers" "True" -process "Synthesize - XST"
project set "Max Fanout" "500" -process "Synthesize - XST"
project set "Number of Clock Buffers" "8" -process "Synthesize - XST"
project set "Register Duplication" "True" -process "Synthesize - XST"
project set "Optimize Instantiated Primitives" "False" -process "Synthesize - XST"
project set "Use Clock Enable" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Set" "Yes" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Yes" -process "Synthesize - XST"
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Equivalent Register Removal" "True" -process "Synthesize - XST"
project set "Optimization Goal" "Speed" -process "Synthesize - XST"
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Library Search Order" "../synth/ddr2.lso" -process "Synthesize - XST"
project set "Keep Hierarchy" "Soft" -process "Synthesize - XST"
project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Read Cores" "True" -process "Synthesize - XST"
project set "Write Timing Constraints" "False" -process "Synthesize - XST"
project set "Cross Clock Analysis" "False" -process "Synthesize - XST"
project set "Hierarchy Separator" "/" -process "Synthesize - XST"
project set "Bus Delimiter" "<>" -process "Synthesize - XST"
project set "Case" "Maintain" -process "Synthesize - XST"
project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
project set "Automatic BRAM Packing" "False" -process "Synthesize - XST"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process Map
project set "Place & Route Effort Level (Overall)" "Standard" -process "Place & Route"
project set "Number of Paths in Error/Verbose Report" "100" -process "Generate Post-Map Static Timing"
project set "Enable Debugging of Serial Mode BitStream" "False" -process "Generate Programming File"
project set "Create Binary Configuration File" "False" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "True" -process "Generate Programming File"
project set "Configuration Rate" "6" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Float" -process "Generate Programming File"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "False" -process "Generate Programming File"
project set "Drive Done Pin High" "False" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project close

51
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/par/vio_coregen.xco vendored Normal file
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##############################################################
#
# Xilinx Core Generator version 11.2
# Date: Fri Jun 12 05:42:56 2009
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = False
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = vhdl
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = False
SET vhdlsim = False
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=7
CSET component_name=vio
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=true
CSET enable_synchronous_input_port=false
CSET enable_synchronous_output_port=false
CSET invert_clock_input=false
CSET synchronous_input_port_width=8
CSET synchronous_output_port_width=8
# END Parameters
GENERATE
# CRC: 66fe39ed

822
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/ddr2.vhd vendored Normal file
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--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.92
-- \ \ Application : MIG
-- / / Filename : ddr2.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:56 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
--Device : Spartan-6
--Design Name : DDR/DDR2/DDR3/LPDDR
--Purpose : This is the design top level. which instantiates top wrapper,
-- test bench top and infrastructure modules.
--Reference :
--Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity ddr2 is
generic
(
C3_P0_MASK_SIZE : integer := 4;
C3_P0_DATA_PORT_SIZE : integer := 32;
C3_P1_MASK_SIZE : integer := 4;
C3_P1_DATA_PORT_SIZE : integer := 32;
C3_MEMCLK_PERIOD : integer := 3000;
-- Memory data transfer clock period.
C3_RST_ACT_LOW : integer := 0;
-- # = 1 for active low reset,
-- # = 0 for active high reset.
C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
-- input clock type DIFFERENTIAL or SINGLE_ENDED.
C3_CALIB_SOFT_IP : string := "TRUE";
-- # = TRUE, Enables the soft calibration logic,
-- # = FALSE, Disables the soft calibration logic.
C3_SIMULATION : string := "FALSE";
-- # = TRUE, Simulating the design. Useful to reduce the simulation time,
-- # = FALSE, Implementing the design.
DEBUG_EN : integer := 0;
-- # = 1, Enable debug signals/controls,
-- = 0, Disable debug signals/controls.
C3_MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
-- The order in which user address is provided to the memory controller,
-- ROW_BANK_COLUMN or BANK_ROW_COLUMN.
C3_NUM_DQ_PINS : integer := 16;
-- External memory data width.
C3_MEM_ADDR_WIDTH : integer := 13;
-- External memory address width.
C3_MEM_BANKADDR_WIDTH : integer := 3
-- External memory bank address width.
);
port
(
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic;
c3_p1_cmd_clk : in std_logic;
c3_p1_cmd_en : in std_logic;
c3_p1_cmd_instr : in std_logic_vector(2 downto 0);
c3_p1_cmd_bl : in std_logic_vector(5 downto 0);
c3_p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p1_cmd_empty : out std_logic;
c3_p1_cmd_full : out std_logic;
c3_p1_wr_clk : in std_logic;
c3_p1_wr_en : in std_logic;
c3_p1_wr_mask : in std_logic_vector(C3_P1_MASK_SIZE - 1 downto 0);
c3_p1_wr_data : in std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_wr_full : out std_logic;
c3_p1_wr_empty : out std_logic;
c3_p1_wr_count : out std_logic_vector(6 downto 0);
c3_p1_wr_underrun : out std_logic;
c3_p1_wr_error : out std_logic;
c3_p1_rd_clk : in std_logic;
c3_p1_rd_en : in std_logic;
c3_p1_rd_data : out std_logic_vector(C3_P1_DATA_PORT_SIZE - 1 downto 0);
c3_p1_rd_full : out std_logic;
c3_p1_rd_empty : out std_logic;
c3_p1_rd_count : out std_logic_vector(6 downto 0);
c3_p1_rd_overflow : out std_logic;
c3_p1_rd_error : out std_logic;
c3_p2_cmd_clk : in std_logic;
c3_p2_cmd_en : in std_logic;
c3_p2_cmd_instr : in std_logic_vector(2 downto 0);
c3_p2_cmd_bl : in std_logic_vector(5 downto 0);
c3_p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p2_cmd_empty : out std_logic;
c3_p2_cmd_full : out std_logic;
c3_p2_wr_clk : in std_logic;
c3_p2_wr_en : in std_logic;
c3_p2_wr_mask : in std_logic_vector(3 downto 0);
c3_p2_wr_data : in std_logic_vector(31 downto 0);
c3_p2_wr_full : out std_logic;
c3_p2_wr_empty : out std_logic;
c3_p2_wr_count : out std_logic_vector(6 downto 0);
c3_p2_wr_underrun : out std_logic;
c3_p2_wr_error : out std_logic;
c3_p2_rd_clk : in std_logic;
c3_p2_rd_en : in std_logic;
c3_p2_rd_data : out std_logic_vector(31 downto 0);
c3_p2_rd_full : out std_logic;
c3_p2_rd_empty : out std_logic;
c3_p2_rd_count : out std_logic_vector(6 downto 0);
c3_p2_rd_overflow : out std_logic;
c3_p2_rd_error : out std_logic;
c3_p3_cmd_clk : in std_logic;
c3_p3_cmd_en : in std_logic;
c3_p3_cmd_instr : in std_logic_vector(2 downto 0);
c3_p3_cmd_bl : in std_logic_vector(5 downto 0);
c3_p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p3_cmd_empty : out std_logic;
c3_p3_cmd_full : out std_logic;
c3_p3_wr_clk : in std_logic;
c3_p3_wr_en : in std_logic;
c3_p3_wr_mask : in std_logic_vector(3 downto 0);
c3_p3_wr_data : in std_logic_vector(31 downto 0);
c3_p3_wr_full : out std_logic;
c3_p3_wr_empty : out std_logic;
c3_p3_wr_count : out std_logic_vector(6 downto 0);
c3_p3_wr_underrun : out std_logic;
c3_p3_wr_error : out std_logic;
c3_p3_rd_clk : in std_logic;
c3_p3_rd_en : in std_logic;
c3_p3_rd_data : out std_logic_vector(31 downto 0);
c3_p3_rd_full : out std_logic;
c3_p3_rd_empty : out std_logic;
c3_p3_rd_count : out std_logic_vector(6 downto 0);
c3_p3_rd_overflow : out std_logic;
c3_p3_rd_error : out std_logic
);
end ddr2;
architecture arc of ddr2 is
component memc3_infrastructure is
generic (
C_RST_ACT_LOW : integer;
C_INPUT_CLK_TYPE : string;
C_CLKOUT0_DIVIDE : integer;
C_CLKOUT1_DIVIDE : integer;
C_CLKOUT2_DIVIDE : integer;
C_CLKOUT3_DIVIDE : integer;
C_CLKFBOUT_MULT : integer;
C_DIVCLK_DIVIDE : integer;
C_INCLK_PERIOD : integer
);
port (
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
sys_clk : in std_logic;
sys_rst_i : in std_logic;
clk0 : out std_logic;
rst0 : out std_logic;
async_rst : out std_logic;
sysclk_2x : out std_logic;
sysclk_2x_180 : out std_logic;
pll_ce_0 : out std_logic;
pll_ce_90 : out std_logic;
pll_lock : out std_logic;
mcb_drp_clk : out std_logic
);
end component;
component memc3_wrapper is
generic (
C_MEMCLK_PERIOD : integer;
C_CALIB_SOFT_IP : string;
C_SIMULATION : string;
C_P0_MASK_SIZE : integer;
C_P0_DATA_PORT_SIZE : integer;
C_P1_MASK_SIZE : integer;
C_P1_DATA_PORT_SIZE : integer;
C_ARB_NUM_TIME_SLOTS : integer;
C_ARB_TIME_SLOT_0 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_1 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_2 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_3 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_4 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_5 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_6 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_7 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_8 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_9 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_10 : bit_vector(11 downto 0);
C_ARB_TIME_SLOT_11 : bit_vector(11 downto 0);
C_MEM_TRAS : integer;
C_MEM_TRCD : integer;
C_MEM_TREFI : integer;
C_MEM_TRFC : integer;
C_MEM_TRP : integer;
C_MEM_TWR : integer;
C_MEM_TRTP : integer;
C_MEM_TWTR : integer;
C_MEM_ADDR_ORDER : string;
C_NUM_DQ_PINS : integer;
C_MEM_TYPE : string;
C_MEM_DENSITY : string;
C_MEM_BURST_LEN : integer;
C_MEM_CAS_LATENCY : integer;
C_MEM_ADDR_WIDTH : integer;
C_MEM_BANKADDR_WIDTH : integer;
C_MEM_NUM_COL_BITS : integer;
C_MEM_DDR1_2_ODS : string;
C_MEM_DDR2_RTT : string;
C_MEM_DDR2_DIFF_DQS_EN : string;
C_MEM_DDR2_3_PA_SR : string;
C_MEM_DDR2_3_HIGH_TEMP_SR : string;
C_MEM_DDR3_CAS_LATENCY : integer;
C_MEM_DDR3_ODS : string;
C_MEM_DDR3_RTT : string;
C_MEM_DDR3_CAS_WR_LATENCY : integer;
C_MEM_DDR3_AUTO_SR : string;
C_MEM_DDR3_DYN_WRT_ODT : string;
C_MEM_MOBILE_PA_SR : string;
C_MEM_MDDR_ODS : string;
C_MC_CALIB_BYPASS : string;
C_MC_CALIBRATION_MODE : string;
C_MC_CALIBRATION_DELAY : string;
C_SKIP_IN_TERM_CAL : integer;
C_SKIP_DYNAMIC_CAL : integer;
C_LDQSP_TAP_DELAY_VAL : integer;
C_LDQSN_TAP_DELAY_VAL : integer;
C_UDQSP_TAP_DELAY_VAL : integer;
C_UDQSN_TAP_DELAY_VAL : integer;
C_DQ0_TAP_DELAY_VAL : integer;
C_DQ1_TAP_DELAY_VAL : integer;
C_DQ2_TAP_DELAY_VAL : integer;
C_DQ3_TAP_DELAY_VAL : integer;
C_DQ4_TAP_DELAY_VAL : integer;
C_DQ5_TAP_DELAY_VAL : integer;
C_DQ6_TAP_DELAY_VAL : integer;
C_DQ7_TAP_DELAY_VAL : integer;
C_DQ8_TAP_DELAY_VAL : integer;
C_DQ9_TAP_DELAY_VAL : integer;
C_DQ10_TAP_DELAY_VAL : integer;
C_DQ11_TAP_DELAY_VAL : integer;
C_DQ12_TAP_DELAY_VAL : integer;
C_DQ13_TAP_DELAY_VAL : integer;
C_DQ14_TAP_DELAY_VAL : integer;
C_DQ15_TAP_DELAY_VAL : integer
);
port (
mcb3_dram_dq : inout std_logic_vector((C_NUM_DQ_PINS-1) downto 0);
mcb3_dram_a : out std_logic_vector((C_MEM_ADDR_WIDTH-1) downto 0);
mcb3_dram_ba : out std_logic_vector((C_MEM_BANKADDR_WIDTH-1) downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
mcb3_dram_udm : out std_logic;
calib_done : out std_logic;
async_rst : in std_logic;
sysclk_2x : in std_logic;
sysclk_2x_180 : in std_logic;
pll_ce_0 : in std_logic;
pll_ce_90 : in std_logic;
pll_lock : in std_logic;
mcb_drp_clk : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
p0_cmd_clk : in std_logic;
p0_cmd_en : in std_logic;
p0_cmd_instr : in std_logic_vector(2 downto 0);
p0_cmd_bl : in std_logic_vector(5 downto 0);
p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
p0_cmd_empty : out std_logic;
p0_cmd_full : out std_logic;
p0_wr_clk : in std_logic;
p0_wr_en : in std_logic;
p0_wr_mask : in std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_wr_data : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_wr_full : out std_logic;
p0_wr_empty : out std_logic;
p0_wr_count : out std_logic_vector(6 downto 0);
p0_wr_underrun : out std_logic;
p0_wr_error : out std_logic;
p0_rd_clk : in std_logic;
p0_rd_en : in std_logic;
p0_rd_data : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_rd_full : out std_logic;
p0_rd_empty : out std_logic;
p0_rd_count : out std_logic_vector(6 downto 0);
p0_rd_overflow : out std_logic;
p0_rd_error : out std_logic;
p1_cmd_clk : in std_logic;
p1_cmd_en : in std_logic;
p1_cmd_instr : in std_logic_vector(2 downto 0);
p1_cmd_bl : in std_logic_vector(5 downto 0);
p1_cmd_byte_addr : in std_logic_vector(29 downto 0);
p1_cmd_empty : out std_logic;
p1_cmd_full : out std_logic;
p1_wr_clk : in std_logic;
p1_wr_en : in std_logic;
p1_wr_mask : in std_logic_vector(C_P1_MASK_SIZE - 1 downto 0);
p1_wr_data : in std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_wr_full : out std_logic;
p1_wr_empty : out std_logic;
p1_wr_count : out std_logic_vector(6 downto 0);
p1_wr_underrun : out std_logic;
p1_wr_error : out std_logic;
p1_rd_clk : in std_logic;
p1_rd_en : in std_logic;
p1_rd_data : out std_logic_vector(C_P1_DATA_PORT_SIZE - 1 downto 0);
p1_rd_full : out std_logic;
p1_rd_empty : out std_logic;
p1_rd_count : out std_logic_vector(6 downto 0);
p1_rd_overflow : out std_logic;
p1_rd_error : out std_logic;
p2_cmd_clk : in std_logic;
p2_cmd_en : in std_logic;
p2_cmd_instr : in std_logic_vector(2 downto 0);
p2_cmd_bl : in std_logic_vector(5 downto 0);
p2_cmd_byte_addr : in std_logic_vector(29 downto 0);
p2_cmd_empty : out std_logic;
p2_cmd_full : out std_logic;
p2_wr_clk : in std_logic;
p2_wr_en : in std_logic;
p2_wr_mask : in std_logic_vector(3 downto 0);
p2_wr_data : in std_logic_vector(31 downto 0);
p2_wr_full : out std_logic;
p2_wr_empty : out std_logic;
p2_wr_count : out std_logic_vector(6 downto 0);
p2_wr_underrun : out std_logic;
p2_wr_error : out std_logic;
p2_rd_clk : in std_logic;
p2_rd_en : in std_logic;
p2_rd_data : out std_logic_vector(31 downto 0);
p2_rd_full : out std_logic;
p2_rd_empty : out std_logic;
p2_rd_count : out std_logic_vector(6 downto 0);
p2_rd_overflow : out std_logic;
p2_rd_error : out std_logic;
p3_cmd_clk : in std_logic;
p3_cmd_en : in std_logic;
p3_cmd_instr : in std_logic_vector(2 downto 0);
p3_cmd_bl : in std_logic_vector(5 downto 0);
p3_cmd_byte_addr : in std_logic_vector(29 downto 0);
p3_cmd_empty : out std_logic;
p3_cmd_full : out std_logic;
p3_wr_clk : in std_logic;
p3_wr_en : in std_logic;
p3_wr_mask : in std_logic_vector(3 downto 0);
p3_wr_data : in std_logic_vector(31 downto 0);
p3_wr_full : out std_logic;
p3_wr_empty : out std_logic;
p3_wr_count : out std_logic_vector(6 downto 0);
p3_wr_underrun : out std_logic;
p3_wr_error : out std_logic;
p3_rd_clk : in std_logic;
p3_rd_en : in std_logic;
p3_rd_data : out std_logic_vector(31 downto 0);
p3_rd_full : out std_logic;
p3_rd_empty : out std_logic;
p3_rd_count : out std_logic_vector(6 downto 0);
p3_rd_overflow : out std_logic;
p3_rd_error : out std_logic;
selfrefresh_enter : in std_logic;
selfrefresh_mode : out std_logic
);
end component;
constant C3_CLKOUT0_DIVIDE : integer := 1;
constant C3_CLKOUT1_DIVIDE : integer := 1;
constant C3_CLKOUT2_DIVIDE : integer := 6;
constant C3_CLKOUT3_DIVIDE : integer := 7;
constant C3_CLKFBOUT_MULT : integer := 20;
constant C3_DIVCLK_DIVIDE : integer := 3;
constant C3_INCLK_PERIOD : integer := 10000; --((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
constant C3_ARB_NUM_TIME_SLOTS : integer := 12;
constant C3_ARB_TIME_SLOT_0 : bit_vector(11 downto 0) := o"0124";
constant C3_ARB_TIME_SLOT_1 : bit_vector(11 downto 0) := o"1240";
constant C3_ARB_TIME_SLOT_2 : bit_vector(11 downto 0) := o"2401";
constant C3_ARB_TIME_SLOT_3 : bit_vector(11 downto 0) := o"4012";
constant C3_ARB_TIME_SLOT_4 : bit_vector(11 downto 0) := o"0124";
constant C3_ARB_TIME_SLOT_5 : bit_vector(11 downto 0) := o"1240";
constant C3_ARB_TIME_SLOT_6 : bit_vector(11 downto 0) := o"2401";
constant C3_ARB_TIME_SLOT_7 : bit_vector(11 downto 0) := o"4012";
constant C3_ARB_TIME_SLOT_8 : bit_vector(11 downto 0) := o"0124";
constant C3_ARB_TIME_SLOT_9 : bit_vector(11 downto 0) := o"1240";
constant C3_ARB_TIME_SLOT_10 : bit_vector(11 downto 0) := o"2401";
constant C3_ARB_TIME_SLOT_11 : bit_vector(11 downto 0) := o"4012";
constant C3_MEM_TRAS : integer := 42500;
constant C3_MEM_TRCD : integer := 12500;
constant C3_MEM_TREFI : integer := 7800000;
constant C3_MEM_TRFC : integer := 127500;
constant C3_MEM_TRP : integer := 12500;
constant C3_MEM_TWR : integer := 15000;
constant C3_MEM_TRTP : integer := 7500;
constant C3_MEM_TWTR : integer := 7500;
constant C3_MEM_TYPE : string := "DDR2";
constant C3_MEM_DENSITY : string := "1Gb";
constant C3_MEM_BURST_LEN : integer := 4;
constant C3_MEM_CAS_LATENCY : integer := 5;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_MEM_DDR1_2_ODS : string := "FULL";
constant C3_MEM_DDR2_RTT : string := "50OHMS";
constant C3_MEM_DDR2_DIFF_DQS_EN : string := "YES";
constant C3_MEM_DDR2_3_PA_SR : string := "FULL";
constant C3_MEM_DDR2_3_HIGH_TEMP_SR : string := "NORMAL";
constant C3_MEM_DDR3_CAS_LATENCY : integer := 6;
constant C3_MEM_DDR3_ODS : string := "DIV6";
constant C3_MEM_DDR3_RTT : string := "DIV2";
constant C3_MEM_DDR3_CAS_WR_LATENCY : integer := 5;
constant C3_MEM_DDR3_AUTO_SR : string := "ENABLED";
constant C3_MEM_DDR3_DYN_WRT_ODT : string := "OFF";
constant C3_MEM_MOBILE_PA_SR : string := "FULL";
constant C3_MEM_MDDR_ODS : string := "FULL";
constant C3_MC_CALIB_BYPASS : string := "NO";
constant C3_MC_CALIBRATION_MODE : string := "CALIBRATION";
constant C3_MC_CALIBRATION_DELAY : string := "HALF";
constant C3_SKIP_IN_TERM_CAL : integer := 0;
constant C3_SKIP_DYNAMIC_CAL : integer := 0;
constant C3_LDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_LDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSP_TAP_DELAY_VAL : integer := 0;
constant C3_UDQSN_TAP_DELAY_VAL : integer := 0;
constant C3_DQ0_TAP_DELAY_VAL : integer := 0;
constant C3_DQ1_TAP_DELAY_VAL : integer := 0;
constant C3_DQ2_TAP_DELAY_VAL : integer := 0;
constant C3_DQ3_TAP_DELAY_VAL : integer := 0;
constant C3_DQ4_TAP_DELAY_VAL : integer := 0;
constant C3_DQ5_TAP_DELAY_VAL : integer := 0;
constant C3_DQ6_TAP_DELAY_VAL : integer := 0;
constant C3_DQ7_TAP_DELAY_VAL : integer := 0;
constant C3_DQ8_TAP_DELAY_VAL : integer := 0;
constant C3_DQ9_TAP_DELAY_VAL : integer := 0;
constant C3_DQ10_TAP_DELAY_VAL : integer := 0;
constant C3_DQ11_TAP_DELAY_VAL : integer := 0;
constant C3_DQ12_TAP_DELAY_VAL : integer := 0;
constant C3_DQ13_TAP_DELAY_VAL : integer := 0;
constant C3_DQ14_TAP_DELAY_VAL : integer := 0;
constant C3_DQ15_TAP_DELAY_VAL : integer := 0;
constant C3_SMALL_DEVICE : string := "FALSE"; -- The parameter is set to TRUE for all packages of xc6slx9 device
-- as most of them cannot fit the complete example design when the
-- Chip scope modules are enabled
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
signal c3_async_rst : std_logic;
signal c3_sysclk_2x : std_logic;
signal c3_sysclk_2x_180 : std_logic;
signal c3_pll_ce_0 : std_logic;
signal c3_pll_ce_90 : std_logic;
signal c3_pll_lock : std_logic;
signal c3_mcb_drp_clk : std_logic;
signal c3_cmp_error : std_logic;
signal c3_cmp_data_valid : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal c3_cmp_data : std_logic_vector(31 downto 0);
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
begin
c3_sys_clk_p <= '0';
c3_sys_clk_n <= '0';
c3_selfrefresh_enter <= '0';
memc3_infrastructure_inst : memc3_infrastructure
generic map
(
C_RST_ACT_LOW => C3_RST_ACT_LOW,
C_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C_CLKOUT0_DIVIDE => C3_CLKOUT0_DIVIDE,
C_CLKOUT1_DIVIDE => C3_CLKOUT1_DIVIDE,
C_CLKOUT2_DIVIDE => C3_CLKOUT2_DIVIDE,
C_CLKOUT3_DIVIDE => C3_CLKOUT3_DIVIDE,
C_CLKFBOUT_MULT => C3_CLKFBOUT_MULT,
C_DIVCLK_DIVIDE => C3_DIVCLK_DIVIDE,
C_INCLK_PERIOD => C3_INCLK_PERIOD
)
port map
(
sys_clk_p => c3_sys_clk_p,
sys_clk_n => c3_sys_clk_n,
sys_clk => c3_sys_clk,
sys_rst_i => c3_sys_rst_i,
clk0 => c3_clk0,
rst0 => c3_rst0,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk
);
-- wrapper instantiation
memc3_wrapper_inst : memc3_wrapper
generic map
(
C_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C_CALIB_SOFT_IP => C3_CALIB_SOFT_IP,
C_SIMULATION => C3_SIMULATION,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_ARB_NUM_TIME_SLOTS => C3_ARB_NUM_TIME_SLOTS,
C_ARB_TIME_SLOT_0 => C3_ARB_TIME_SLOT_0,
C_ARB_TIME_SLOT_1 => C3_ARB_TIME_SLOT_1,
C_ARB_TIME_SLOT_2 => C3_ARB_TIME_SLOT_2,
C_ARB_TIME_SLOT_3 => C3_ARB_TIME_SLOT_3,
C_ARB_TIME_SLOT_4 => C3_ARB_TIME_SLOT_4,
C_ARB_TIME_SLOT_5 => C3_ARB_TIME_SLOT_5,
C_ARB_TIME_SLOT_6 => C3_ARB_TIME_SLOT_6,
C_ARB_TIME_SLOT_7 => C3_ARB_TIME_SLOT_7,
C_ARB_TIME_SLOT_8 => C3_ARB_TIME_SLOT_8,
C_ARB_TIME_SLOT_9 => C3_ARB_TIME_SLOT_9,
C_ARB_TIME_SLOT_10 => C3_ARB_TIME_SLOT_10,
C_ARB_TIME_SLOT_11 => C3_ARB_TIME_SLOT_11,
C_MEM_TRAS => C3_MEM_TRAS,
C_MEM_TRCD => C3_MEM_TRCD,
C_MEM_TREFI => C3_MEM_TREFI,
C_MEM_TRFC => C3_MEM_TRFC,
C_MEM_TRP => C3_MEM_TRP,
C_MEM_TWR => C3_MEM_TWR,
C_MEM_TRTP => C3_MEM_TRTP,
C_MEM_TWTR => C3_MEM_TWTR,
C_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_TYPE => C3_MEM_TYPE,
C_MEM_DENSITY => C3_MEM_DENSITY,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_CAS_LATENCY => C3_MEM_CAS_LATENCY,
C_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_MEM_DDR1_2_ODS => C3_MEM_DDR1_2_ODS,
C_MEM_DDR2_RTT => C3_MEM_DDR2_RTT,
C_MEM_DDR2_DIFF_DQS_EN => C3_MEM_DDR2_DIFF_DQS_EN,
C_MEM_DDR2_3_PA_SR => C3_MEM_DDR2_3_PA_SR,
C_MEM_DDR2_3_HIGH_TEMP_SR => C3_MEM_DDR2_3_HIGH_TEMP_SR,
C_MEM_DDR3_CAS_LATENCY => C3_MEM_DDR3_CAS_LATENCY,
C_MEM_DDR3_ODS => C3_MEM_DDR3_ODS,
C_MEM_DDR3_RTT => C3_MEM_DDR3_RTT,
C_MEM_DDR3_CAS_WR_LATENCY => C3_MEM_DDR3_CAS_WR_LATENCY,
C_MEM_DDR3_AUTO_SR => C3_MEM_DDR3_AUTO_SR,
C_MEM_DDR3_DYN_WRT_ODT => C3_MEM_DDR3_DYN_WRT_ODT,
C_MEM_MOBILE_PA_SR => C3_MEM_MOBILE_PA_SR,
C_MEM_MDDR_ODS => C3_MEM_MDDR_ODS,
C_MC_CALIB_BYPASS => C3_MC_CALIB_BYPASS,
C_MC_CALIBRATION_MODE => C3_MC_CALIBRATION_MODE,
C_MC_CALIBRATION_DELAY => C3_MC_CALIBRATION_DELAY,
C_SKIP_IN_TERM_CAL => C3_SKIP_IN_TERM_CAL,
C_SKIP_DYNAMIC_CAL => C3_SKIP_DYNAMIC_CAL,
C_LDQSP_TAP_DELAY_VAL => C3_LDQSP_TAP_DELAY_VAL,
C_LDQSN_TAP_DELAY_VAL => C3_LDQSN_TAP_DELAY_VAL,
C_UDQSP_TAP_DELAY_VAL => C3_UDQSP_TAP_DELAY_VAL,
C_UDQSN_TAP_DELAY_VAL => C3_UDQSN_TAP_DELAY_VAL,
C_DQ0_TAP_DELAY_VAL => C3_DQ0_TAP_DELAY_VAL,
C_DQ1_TAP_DELAY_VAL => C3_DQ1_TAP_DELAY_VAL,
C_DQ2_TAP_DELAY_VAL => C3_DQ2_TAP_DELAY_VAL,
C_DQ3_TAP_DELAY_VAL => C3_DQ3_TAP_DELAY_VAL,
C_DQ4_TAP_DELAY_VAL => C3_DQ4_TAP_DELAY_VAL,
C_DQ5_TAP_DELAY_VAL => C3_DQ5_TAP_DELAY_VAL,
C_DQ6_TAP_DELAY_VAL => C3_DQ6_TAP_DELAY_VAL,
C_DQ7_TAP_DELAY_VAL => C3_DQ7_TAP_DELAY_VAL,
C_DQ8_TAP_DELAY_VAL => C3_DQ8_TAP_DELAY_VAL,
C_DQ9_TAP_DELAY_VAL => C3_DQ9_TAP_DELAY_VAL,
C_DQ10_TAP_DELAY_VAL => C3_DQ10_TAP_DELAY_VAL,
C_DQ11_TAP_DELAY_VAL => C3_DQ11_TAP_DELAY_VAL,
C_DQ12_TAP_DELAY_VAL => C3_DQ12_TAP_DELAY_VAL,
C_DQ13_TAP_DELAY_VAL => C3_DQ13_TAP_DELAY_VAL,
C_DQ14_TAP_DELAY_VAL => C3_DQ14_TAP_DELAY_VAL,
C_DQ15_TAP_DELAY_VAL => C3_DQ15_TAP_DELAY_VAL
)
port map
(
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_dm => mcb3_dram_dm,
mcb3_dram_udqs => mcb3_dram_udqs,
mcb3_dram_udqs_n => mcb3_dram_udqs_n,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udm => mcb3_dram_udm,
calib_done => c3_calib_done,
async_rst => c3_async_rst,
sysclk_2x => c3_sysclk_2x,
sysclk_2x_180 => c3_sysclk_2x_180,
pll_ce_0 => c3_pll_ce_0,
pll_ce_90 => c3_pll_ce_90,
pll_lock => c3_pll_lock,
mcb_drp_clk => c3_mcb_drp_clk,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
p0_cmd_clk => c3_p0_cmd_clk,
p0_cmd_en => c3_p0_cmd_en,
p0_cmd_instr => c3_p0_cmd_instr,
p0_cmd_bl => c3_p0_cmd_bl,
p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
p0_cmd_empty => c3_p0_cmd_empty,
p0_cmd_full => c3_p0_cmd_full,
p0_wr_clk => c3_p0_wr_clk,
p0_wr_en => c3_p0_wr_en,
p0_wr_mask => c3_p0_wr_mask,
p0_wr_data => c3_p0_wr_data,
p0_wr_full => c3_p0_wr_full,
p0_wr_empty => c3_p0_wr_empty,
p0_wr_count => c3_p0_wr_count,
p0_wr_underrun => c3_p0_wr_underrun,
p0_wr_error => c3_p0_wr_error,
p0_rd_clk => c3_p0_rd_clk,
p0_rd_en => c3_p0_rd_en,
p0_rd_data => c3_p0_rd_data,
p0_rd_full => c3_p0_rd_full,
p0_rd_empty => c3_p0_rd_empty,
p0_rd_count => c3_p0_rd_count,
p0_rd_overflow => c3_p0_rd_overflow,
p0_rd_error => c3_p0_rd_error,
p1_cmd_clk => c3_p1_cmd_clk,
p1_cmd_en => c3_p1_cmd_en,
p1_cmd_instr => c3_p1_cmd_instr,
p1_cmd_bl => c3_p1_cmd_bl,
p1_cmd_byte_addr => c3_p1_cmd_byte_addr,
p1_cmd_empty => c3_p1_cmd_empty,
p1_cmd_full => c3_p1_cmd_full,
p1_wr_clk => c3_p1_wr_clk,
p1_wr_en => c3_p1_wr_en,
p1_wr_mask => c3_p1_wr_mask,
p1_wr_data => c3_p1_wr_data,
p1_wr_full => c3_p1_wr_full,
p1_wr_empty => c3_p1_wr_empty,
p1_wr_count => c3_p1_wr_count,
p1_wr_underrun => c3_p1_wr_underrun,
p1_wr_error => c3_p1_wr_error,
p1_rd_clk => c3_p1_rd_clk,
p1_rd_en => c3_p1_rd_en,
p1_rd_data => c3_p1_rd_data,
p1_rd_full => c3_p1_rd_full,
p1_rd_empty => c3_p1_rd_empty,
p1_rd_count => c3_p1_rd_count,
p1_rd_overflow => c3_p1_rd_overflow,
p1_rd_error => c3_p1_rd_error,
p2_cmd_clk => c3_p2_cmd_clk,
p2_cmd_en => c3_p2_cmd_en,
p2_cmd_instr => c3_p2_cmd_instr,
p2_cmd_bl => c3_p2_cmd_bl,
p2_cmd_byte_addr => c3_p2_cmd_byte_addr,
p2_cmd_empty => c3_p2_cmd_empty,
p2_cmd_full => c3_p2_cmd_full,
p2_wr_clk => c3_p2_wr_clk,
p2_wr_en => c3_p2_wr_en,
p2_wr_mask => c3_p2_wr_mask,
p2_wr_data => c3_p2_wr_data,
p2_wr_full => c3_p2_wr_full,
p2_wr_empty => c3_p2_wr_empty,
p2_wr_count => c3_p2_wr_count,
p2_wr_underrun => c3_p2_wr_underrun,
p2_wr_error => c3_p2_wr_error,
p2_rd_clk => c3_p2_rd_clk,
p2_rd_en => c3_p2_rd_en,
p2_rd_data => c3_p2_rd_data,
p2_rd_full => c3_p2_rd_full,
p2_rd_empty => c3_p2_rd_empty,
p2_rd_count => c3_p2_rd_count,
p2_rd_overflow => c3_p2_rd_overflow,
p2_rd_error => c3_p2_rd_error,
p3_cmd_clk => c3_p3_cmd_clk,
p3_cmd_en => c3_p3_cmd_en,
p3_cmd_instr => c3_p3_cmd_instr,
p3_cmd_bl => c3_p3_cmd_bl,
p3_cmd_byte_addr => c3_p3_cmd_byte_addr,
p3_cmd_empty => c3_p3_cmd_empty,
p3_cmd_full => c3_p3_cmd_full,
p3_wr_clk => c3_p3_wr_clk,
p3_wr_en => c3_p3_wr_en,
p3_wr_mask => c3_p3_wr_mask,
p3_wr_data => c3_p3_wr_data,
p3_wr_full => c3_p3_wr_full,
p3_wr_empty => c3_p3_wr_empty,
p3_wr_count => c3_p3_wr_count,
p3_wr_underrun => c3_p3_wr_underrun,
p3_wr_error => c3_p3_wr_error,
p3_rd_clk => c3_p3_rd_clk,
p3_rd_en => c3_p3_rd_en,
p3_rd_data => c3_p3_rd_data,
p3_rd_full => c3_p3_rd_full,
p3_rd_empty => c3_p3_rd_empty,
p3_rd_count => c3_p3_rd_count,
p3_rd_overflow => c3_p3_rd_overflow,
p3_rd_error => c3_p3_rd_error,
selfrefresh_enter => c3_selfrefresh_enter,
selfrefresh_mode => c3_selfrefresh_mode
);
end arc;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_controller.vhd vendored Executable file
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@@ -0,0 +1,372 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 02/06/09: Initial version for MIG wrapper.
-- 1.1: 02/01/09: updates to indentations.
-- 1.2: 02/12/09: changed non-blocking assignments to blocking ones
-- for state machine always block. Also, assigned
-- intial value to load_shift_n to avoid latch
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues
-- to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- (* FSM_ENCODING="GRAY" *) reg [2:0] state, nextstate;
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
-- added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic
);
end entity iodrp_controller;
architecture trans of iodrp_controller is
constant READY : std_logic_vector(2 downto 0) := "000";
constant DECIDE : std_logic_vector(2 downto 0) := "001";
constant ADDR_PHASE : std_logic_vector(2 downto 0) := "010";
constant ADDR_TO_DATA_GAP : std_logic_vector(2 downto 0) := "011";
constant ADDR_TO_DATA_GAP2 : std_logic_vector(2 downto 0) := "100";
constant ADDR_TO_DATA_GAP3 : std_logic_vector(2 downto 0) := "101";
constant DATA_PHASE : std_logic_vector(2 downto 0) := "110";
constant ALMOST_READY : std_logic_vector(2 downto 0) := "111";
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(7 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal capture_read_data : std_logic;
signal state : std_logic_vector(2 downto 0);
signal nextstate : std_logic_vector(2 downto 0);
signal data_out_mux : std_logic_vector(7 downto 0);
signal DRP_SDI_pre : std_logic;
signal ALMOST_READY_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
begin
--synthesis translate_off
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY => -- case(state)
-- state_ascii <= "ALMOST_READY";
-- when others =>
-- null;
-- end case;
-- end process;
--synthesis translate_on
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when (state = READY) else '0';
data_out_mux <= memcell_addr_reg when (addr_data_sel_n = '1') else
data_reg;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "00000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= (DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (not(sync_rst)) = '1') then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
-- capture_read_data <= 1'b0;
read_data <= "00000000";
else
-- capture_read_data <= (state == DATA_PHASE);
-- if(capture_read_data)
if (state = ALMOST_READY) then
-- else
-- read_data <= read_data;
read_data <= shift_through_reg;
end if;
end if;
end if;
end process;
ALMOST_READY_ST <= '1' when state = ALMOST_READY else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD <= ADDR_PHASE_ST1;
DRP_CS <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
-- assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
-- assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI <= shift_through_reg(0); -- The new read method only requires that we shift out the address and the write data
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the read access.
when ADDR_PHASE =>
if (BIT_CNT7 = '1') then
if (rd_not_write_reg = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
nextstate <= READY;
when others =>
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;

517
fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/iodrp_mcb_controller.vhd vendored Executable file
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@@ -0,0 +1,517 @@
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: iodrp_mcb_controller.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:17:25 $
-- \ \ / \ Date Created: Mon Feb 9 2009
-- \___\/\___\
--
--Device: Spartan6
--Design Name: DDR/DDR2/DDR3/LPDDR
--Purpose: Xilinx reference design for IODRP controller for v0.9 device
--
--Reference:
--
-- Revision: Date: Comment
-- 1.0: 03/19/09: Initial version for IODRP_MCB read operations.
-- 1.1: 04/03/09: SLH - Added left shift for certain IOI's
-- 1.2: 02/14/11: Change FSM encoding from one-hot to gray to match Verilog version.
-- End Revision
--*******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity iodrp_mcb_controller is
--output to IODRP SDI pin
--input from IODRP SDO pin
-- Register where memcell_address is captured during the READY state
-- Register which stores the write data until it is ready to be shifted out
-- The shift register which shifts out SDO and shifts in SDI.
-- This register is loaded before the address or data phase, but continues to shift for a writeback of read data
-- The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
-- The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
-- The counter for which bit is being shifted during address or data phase
-- This is set after the first address phase has executed
-- The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
--added so that DRP_SDI output is only active when DRP_CS is active
port (
memcell_address : in std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
read_data : out std_logic_vector(7 downto 0);
rd_not_write : in std_logic;
cmd_valid : in std_logic;
rdy_busy_n : out std_logic;
use_broadcast : in std_logic;
drp_ioi_addr : in std_logic_vector(4 downto 0);
sync_rst : in std_logic;
DRP_CLK : in std_logic;
DRP_CS : out std_logic;
DRP_SDI : out std_logic;
DRP_ADD : out std_logic;
DRP_BKST : out std_logic;
DRP_SDO : in std_logic;
MCB_UIREAD : out std_logic
);
end entity iodrp_mcb_controller;
architecture trans of iodrp_mcb_controller is
type StType is (
READY,
DECIDE ,
ADDR_PHASE ,
ADDR_TO_DATA_GAP ,
ADDR_TO_DATA_GAP2,
ADDR_TO_DATA_GAP3,
DATA_PHASE ,
ALMOST_READY ,
ALMOST_READY2 ,
ALMOST_READY3
);
constant IOI_DQ0 : std_logic_vector(4 downto 0) := "00001";
constant IOI_DQ1 : std_logic_vector(4 downto 0) := "00000";
constant IOI_DQ2 : std_logic_vector(4 downto 0) := "00011";
constant IOI_DQ3 : std_logic_vector(4 downto 0) := "00010";
constant IOI_DQ4 : std_logic_vector(4 downto 0) := "00101";
constant IOI_DQ5 : std_logic_vector(4 downto 0) := "00100";
constant IOI_DQ6 : std_logic_vector(4 downto 0) := "00111";
constant IOI_DQ7 : std_logic_vector(4 downto 0) := "00110";
constant IOI_DQ8 : std_logic_vector(4 downto 0) := "01001";
constant IOI_DQ9 : std_logic_vector(4 downto 0) := "01000";
constant IOI_DQ10 : std_logic_vector(4 downto 0) := "01011";
constant IOI_DQ11 : std_logic_vector(4 downto 0) := "01010";
constant IOI_DQ12 : std_logic_vector(4 downto 0) := "01101";
constant IOI_DQ13 : std_logic_vector(4 downto 0) := "01100";
constant IOI_DQ14 : std_logic_vector(4 downto 0) := "01111";
constant IOI_DQ15 : std_logic_vector(4 downto 0) := "01110";
constant IOI_UDQS_CLK : std_logic_vector(4 downto 0) := "11101";
constant IOI_UDQS_PIN : std_logic_vector(4 downto 0) := "11100";
constant IOI_LDQS_CLK : std_logic_vector(4 downto 0) := "11111";
constant IOI_LDQS_PIN : std_logic_vector(4 downto 0) := "11110";
signal memcell_addr_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal shift_through_reg : std_logic_vector(8 downto 0);
signal load_shift_n : std_logic;
signal addr_data_sel_n : std_logic;
signal bit_cnt : std_logic_vector(2 downto 0);
signal rd_not_write_reg : std_logic;
signal AddressPhase : std_logic;
signal DRP_CS_pre : std_logic;
signal extra_cs : std_logic;
signal state,nextstate : StType;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "gray";
attribute fsm_encoding of nextstate : signal is "gray";
signal data_out : std_logic_vector(8 downto 0);
signal data_out_mux : std_logic_vector(8 downto 0);
signal DRP_SDI_pre : std_logic;
--synthesis translate_off
signal state_ascii : std_logic_vector(32 * 8 - 1 downto 0);
-- case(state)
--synthesis translate_on
-- The changes below are to compensate for an issue with 1.0 silicon.
-- It may still be necessary to add a clock cycle to the ADD and CS signals
--`define DRP_v1_0_FIX // Uncomment out this line for synthesis
procedure shift_n_expand(
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(8 downto 0)) is
variable data_out_xilinx2 : std_logic_vector(8 downto 0);
begin
if ((data_in(0)) = '1') then
data_out_xilinx2(1 downto 0) := "11";
else
data_out_xilinx2(1 downto 0) := "00";
end if;
if (data_in(1 downto 0) = "10") then
data_out_xilinx2(2 downto 1) := "11";
else
data_out_xilinx2(2 downto 1) := (data_in(1) & data_out_xilinx2(1));
end if;
if (data_in(2 downto 1) = "10") then
data_out_xilinx2(3 downto 2) := "11";
else
data_out_xilinx2(3 downto 2) := (data_in(2) & data_out_xilinx2(2));
end if;
if (data_in(3 downto 2) = "10") then
data_out_xilinx2(4 downto 3) := "11";
else
data_out_xilinx2(4 downto 3) := (data_in(3) & data_out_xilinx2(3));
end if;
if (data_in(4 downto 3) = "10") then
data_out_xilinx2(5 downto 4) := "11";
else
data_out_xilinx2(5 downto 4) := (data_in(4) & data_out_xilinx2(4));
end if;
if (data_in(5 downto 4) = "10") then
data_out_xilinx2(6 downto 5) := "11";
else
data_out_xilinx2(6 downto 5) := (data_in(5) & data_out_xilinx2(5));
end if;
if (data_in(6 downto 5) = "10") then
data_out_xilinx2(7 downto 6) := "11";
else
data_out_xilinx2(7 downto 6) := (data_in(6) & data_out_xilinx2(6));
end if;
if (data_in(7 downto 6) = "10") then
data_out_xilinx2(8 downto 7) := "11";
else
data_out_xilinx2(8 downto 7) := (data_in(7) & data_out_xilinx2(7));
end if;
end shift_n_expand;
-- Declare intermediate signals for referenced outputs
signal DRP_CS_xilinx1 : std_logic;
signal DRP_ADD_xilinx0 : std_logic;
signal ALMOST_READY2_ST : std_logic;
signal ADDR_PHASE_ST : std_logic;
signal BIT_CNT7 : std_logic;
signal ADDR_PHASE_ST1 : std_logic;
signal DATA_PHASE_ST : std_logic;
begin
-- Drive referenced outputs
DRP_CS <= DRP_CS_xilinx1;
DRP_ADD <= DRP_ADD_xilinx0;
-- process (state)
-- begin
-- case state is
-- when READY =>
-- state_ascii <= "READY";
-- when DECIDE =>
-- state_ascii <= "DECIDE";
-- when ADDR_PHASE =>
-- state_ascii <= "ADDR_PHASE";
-- when ADDR_TO_DATA_GAP =>
-- state_ascii <= "ADDR_TO_DATA_GAP";
-- when ADDR_TO_DATA_GAP2 =>
-- state_ascii <= "ADDR_TO_DATA_GAP2";
-- when ADDR_TO_DATA_GAP3 =>
-- state_ascii <= "ADDR_TO_DATA_GAP3";
-- when DATA_PHASE =>
-- state_ascii <= "DATA_PHASE";
-- when ALMOST_READY =>
-- state_ascii <= "ALMOST_READY";
-- when ALMOST_READY2 =>
-- state_ascii <= "ALMOST_READY2";
-- when ALMOST_READY3 =>
-- state_ascii <= "ALMOST_READY3";
-- when others =>
-- null;
-- end case;
-- end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (state = READY) then
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end if;
end if;
end process;
rdy_busy_n <= '1' when state = READY else '0';
process (drp_ioi_addr, data_out)
begin
case drp_ioi_addr is
when IOI_DQ0 =>
data_out_mux <= data_out;
when IOI_DQ1 =>
data_out_mux <= data_out;
when IOI_DQ2 =>
data_out_mux <= data_out;
when IOI_DQ3 =>
data_out_mux <= data_out;
when IOI_DQ4 =>
data_out_mux <= data_out;
when IOI_DQ5 =>
data_out_mux <= data_out;
when IOI_DQ6 =>
data_out_mux <= data_out;
when IOI_DQ7 =>
data_out_mux <= data_out;
when IOI_DQ8 =>
data_out_mux <= data_out;
when IOI_DQ9 =>
data_out_mux <= data_out;
when IOI_DQ10 =>
data_out_mux <= data_out;
when IOI_DQ11 =>
data_out_mux <= data_out;
when IOI_DQ12 =>
data_out_mux <= data_out;
when IOI_DQ13 =>
data_out_mux <= data_out;
when IOI_DQ14 =>
data_out_mux <= data_out;
when IOI_DQ15 =>
data_out_mux <= data_out;
when IOI_UDQS_CLK =>
data_out_mux <= data_out;
when IOI_UDQS_PIN =>
data_out_mux <= data_out;
when IOI_LDQS_CLK =>
data_out_mux <= data_out;
when IOI_LDQS_PIN =>
data_out_mux <= data_out;
when others =>
data_out_mux <= data_out;
end case;
end process;
data_out <= ('0' & memcell_addr_reg) when (addr_data_sel_n = '1') else
('0' & data_reg);
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
shift_through_reg <= "000000000";
else
if (load_shift_n = '1') then --Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= ('0' & DRP_SDO & shift_through_reg(7 downto 1));
end if;
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (((state = ADDR_PHASE) or (state = DATA_PHASE)) and (sync_rst = '0')) then
bit_cnt <= bit_cnt + "001";
else
bit_cnt <= "000";
end if;
end if;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
read_data <= "00000000";
else
if (state = ALMOST_READY3) then
read_data <= shift_through_reg(7 downto 0);
end if;
end if;
end if;
end process;
ALMOST_READY2_ST <= '1' when state = ALMOST_READY2 else '0';
ADDR_PHASE_ST <= '1' when state = ADDR_PHASE else '0';
BIT_CNT7 <= '1' when bit_cnt = "111" else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
AddressPhase <= '0';
else
if (AddressPhase = '1') then
-- Keep it set until we finish the cycle
AddressPhase <= AddressPhase and (not ALMOST_READY2_ST);
else
-- set the address phase when ever we finish the address phase
AddressPhase <= (ADDR_PHASE_ST and BIT_CNT7);
end if;
end if;
end if;
end process;
ADDR_PHASE_ST1 <= '1' when nextstate = ADDR_PHASE else '0';
DATA_PHASE_ST <= '1' when nextstate = DATA_PHASE else '0';
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
DRP_ADD_xilinx0 <= ADDR_PHASE_ST1;
-- DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
DRP_CS_xilinx1 <= ADDR_PHASE_ST1 or DATA_PHASE_ST;
MCB_UIREAD <= DATA_PHASE_ST and rd_not_write_reg;
if (state = READY) then
DRP_BKST <= use_broadcast;
end if;
end if;
end process;
DRP_SDI_pre <= shift_through_reg(0) when (DRP_CS_xilinx1 = '1') else --if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
'0';
DRP_SDI <= DRP_SDO when ((rd_not_write_reg and DRP_CS_xilinx1 and not(DRP_ADD_xilinx0)) = '1') else --If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
DRP_SDI_pre;
process (state, cmd_valid, bit_cnt, rd_not_write_reg, AddressPhase,BIT_CNT7)
begin
addr_data_sel_n <= '0';
load_shift_n <= '0';
case state is
when READY =>
load_shift_n <= '0';
if (cmd_valid = '1') then
nextstate <= DECIDE;
else
nextstate <= READY;
end if;
when DECIDE =>
load_shift_n <= '1';
addr_data_sel_n <= '1';
nextstate <= ADDR_PHASE;
-- After the second pass go to end of statemachine
-- execute a second address phase for the alternative access method.
when ADDR_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
if (('1' and rd_not_write_reg) = '1') then
if (AddressPhase = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DECIDE;
end if;
else
nextstate <= ADDR_TO_DATA_GAP;
end if;
else
nextstate <= ADDR_PHASE;
end if;
when ADDR_TO_DATA_GAP =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP2;
when ADDR_TO_DATA_GAP2 =>
load_shift_n <= '1';
nextstate <= ADDR_TO_DATA_GAP3;
when ADDR_TO_DATA_GAP3 =>
load_shift_n <= '1';
nextstate <= DATA_PHASE;
when DATA_PHASE =>
load_shift_n <= '0';
if (BIT_CNT7 = '1') then
nextstate <= ALMOST_READY;
else
nextstate <= DATA_PHASE;
end if;
when ALMOST_READY =>
load_shift_n <= '0';
nextstate <= ALMOST_READY2;
when ALMOST_READY2 =>
load_shift_n <= '0';
nextstate <= ALMOST_READY3;
when ALMOST_READY3 =>
load_shift_n <= '0';
nextstate <= READY;
when others =>
load_shift_n <= '0';
nextstate <= READY;
end case;
end process;
process (DRP_CLK)
begin
if (DRP_CLK'event and DRP_CLK = '1') then
if (sync_rst = '1') then
state <= READY;
else
state <= nextstate;
end if;
end if;
end process;
end architecture trans;

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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_raw_wrapper.vhd vendored Executable file
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fpga/src/vendor/xilinx/atlys_ddr2/ddr2/user_design/rtl/mcb_soft_calibration.vhd vendored Executable file
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